The present disclosure relates to a full-bridge class D amplifier comprising a first and second half-bridge circuit, wherein each half-bridge comprises a half-bridge output terminal between a high-side switch and a low-side switch. Wherein the first and second half-bridge circuits are controlled by a respective control signal to operate in differential mode with a predetermined switching frequency and wherein each half-bridge circuit further comprises an output terminal inductor connected between the half-bridge output terminal and ground. The amplifier further comprises a first and second coil coupled to form a common mode choke, wherein the first half-bridge output terminal is connected to an input terminal of the first coil, and wherein the second half-bridge output terminal is connected to an input terminal of the second coil .

A power amplifier includes a carrier amplifier that operates from when an input signal is small, a peak amplifier that starts to operate when the input signal becomes large, a phase adjusting circuit that adjusts phases of an output of the carrier amplifier and an output of the peak amplifier, an impedance transforming line that transforms a load of the carrier amplifier when the input signal is small, and has a characteristic impedance close to an optimum load impedance of the carrier amplifier, and a circuit that is arranged between the output of the carrier amplifier and the impedance transforming line and reduces an output capacitance of the carrier amplifier.

A power amplifier includes a carrier amplifier that operates from when an input signal is small, a peak amplifier that starts to operate when the input signal becomes large, a phase adjusting circuit that adjusts phases of an output of the carrier amplifier and an output of the peak amplifier, an impedance transforming line that transforms a load of the carrier amplifier when the input signal is small, and has a characteristic impedance close to an optimum load impedance of the carrier amplifier, and a circuit that is arranged between the output of the carrier amplifier and the impedance transforming line and reduces an output capacitance of the carrier amplifier.

er amplifier includes a power splitter that splits a first signal into a second signal and a third signal delayed from the second signal by about 90, a first amplifier that outputs a fourth signal by amplifying the second signal when a power level of the first signal equals/exceeds a first level, a second amplifier that outputs a fifth signal by amplifying the third signal when the power level of the first signal equals/exceeds a second level higher than the first level, a first phase shifter that receives the fourth signal and outputs a sixth signal delayed from the fourth signal by about 45, a second phase shifter that receives the fifth signal and outputs a seventh signal advanced from the fifth signal by about 45, and a combining unit that outputs an amplified signal of the first signal by combining the sixth and seventh signals.

er amplifier includes a power splitter that splits a first signal into a second signal and a third signal delayed from the second signal by about 90, a first amplifier that outputs a fourth signal by amplifying the second signal when a power level of the first signal equals/exceeds a first level, a second amplifier that outputs a fifth signal by amplifying the third signal when the power level of the first signal equals/exceeds a second level higher than the first level, a first phase shifter that receives the fourth signal and outputs a sixth signal delayed from the fourth signal by about 45, a second phase shifter that receives the fifth signal and outputs a seventh signal advanced from the fifth signal by about 45, and a combining unit that outputs an amplified signal of the first signal by combining the sixth and seventh signals.

A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal delayed from the second signal by about 90, a first amplifier that outputs a fourth signal by amplifying the second signal when a power level of the first signal equals/exceeds a first level, a second amplifier that outputs a fifth signal by amplifying the third signal when the power level of the first signal equals/exceeds a second level higher than the first level, a first phase shifter that receives the fourth signal and outputs a sixth signal delayed from the fourth signal by about 45, a second phase shifter that receives the fifth signal and outputs a seventh signal advanced from the fifth signal by about 45, and a combining unit that outputs an amplified signal of the first signal by combining the sixth and seventh signals.