The present invention provides an amplifier circuit, wherein the amplifier circuit includes a DAC, an output stage and a detector. In the operations of the amplifier circuit, the DAC is arranged for performing a digital-to-analog converting operation upon a digital input signal to generate an analog signal, the output stage is arranged for receiving the analog signal to generate an output signal, and the detector is arranged for detecting a characteristic of the input signal, and referring to the characteristic of the input signal to generate at least one control signal to adjust the output stage at a zero-crossing point of the output signal.

The present invention provides an amplifier circuit, wherein the amplifier circuit includes a DAC, an output stage and a detector. In the operations of the amplifier circuit, the DAC is arranged for performing a digital-to-analog converting operation upon a digital input signal to generate an analog signal, the output stage is arranged for receiving the analog signal to generate an output signal, and the detector is arranged for detecting a characteristic of the input signal, and referring to the characteristic of the input signal to generate at least one control signal to adjust the output stage at a zero-crossing point of the output signal.

An amplifier arrangement comprising first and second power amplifiers (T1, T2) having drains connected to positive and negative drive voltages, respectively, and gates connected to an input signal. The arrangement further comprises first and second current sensors (1, 2) for detecting first and second drain currents from the power amplifiers, processing circuitry (3) adapted to identify the smallest drain current, and a feedback control loop (5) and means for driving a bias current dependent on a feedback signal through a resistor connected between the input signal and the gate of an inactive one of the first and second power amplifiers. The control loop will keep the idle current constant in the transistor with the lowest current (the inactive transistor). Thereby, the current running in the transistor which does not deliver current to the load will be fixed at a desired value.

An amplifier arrangement comprising first and second power amplifiers (T1, T2) having drains connected to positive and negative drive voltages, respectively, and gates connected to an input signal. The arrangement further comprises first and second current sensors (1, 2) for detecting first and second drain currents from the power amplifiers, processing circuitry (3) adapted to identify the smallest drain current, and a feedback control loop (5) and means for driving a bias current dependent on a feedback signal through a resistor connected between the input signal and the gate of an inactive one of the first and second power amplifiers. The control loop will keep the idle current constant in the transistor with the lowest current (the inactive transistor). Thereby, the current running in the transistor which does not deliver current to the load will be fixed at a desired value.