A logarithmic amplifier circuit includes an adaptive gain amplifier circuit and a transistor. The adaptive gain amplifier circuit includes a gain stage and a diode. The gain stage includes an input terminal, and an output terminal. The diode includes a cathode terminal coupled to the output terminal, and an anode terminal coupled to a common terminal. The transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the common terminal, and a third terminal coupled to the output terminal.

An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.

An apparatus includes a load pair including a first transistor and a second transistor, a common mode feedback circuit comprising a first common mode feedback transistor and a second common mode feedback transistor, wherein a drain of the first common mode feedback transistor is coupled to a source of the first transistor, and a gate of the first common mode feedback transistor is coupled to a drain of the first transistor, and a drain of the second common mode feedback transistor is coupled to a source of the second transistor, and a gate of the second common mode feedback transistor is coupled to a drain of the second transistor, and an offset cancellation stage coupled to outputs of the load pair.

A logarithmic amplifier circuit includes an adaptive gain amplifier circuit and a transistor. The adaptive gain amplifier circuit includes a gain stage and a diode. The gain stage includes an input terminal, and an output terminal. The diode includes a cathode terminal coupled to the output terminal, and an anode terminal coupled to a common terminal. The transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the common terminal, and a third terminal coupled to the output terminal.

In some embodiments, a differential input stage comprises a first n-type metal oxide semiconductor transistor (NMOS) pair coupled to a first input and a second input, a second NMOS pair coupled to the first input, a first output node, the second input, and a second output node, a first diode coupled to the first NMOS pair and the first output node, a second diode coupled to the first NMOS pair and the second output node, and a cascaded current source coupled to the first NMOS pair and the second NMOS pair.

An amplifier that amplifies a differential signal includes first and second input terminals for receiving two input signals; first and second diodes each including an anode and a cathode, the anodes being electrically connected to the first and second input terminals; first and second bias current sources being respectively electrically connected to the cathodes of the first and second diodes; an operational amplifier connected to the cathode of the first diode and the cathode of the second diode and configured to amplify a differential signal between signals generated at the cathodes of the first and second diodes; a capacitive element being electrically connected between an input and an output of the operational amplifier; and a differential amplifier provided between the operational amplifier and the first and second input terminals and configured to amplify the two input signals. The first and second bias current sources include a current mirror circuit.

In some embodiments, a differential input stage comprises a first n-type metal oxide semiconductor transistor (NMOS) pair coupled to a first input and a second input, a second NMOS pair coupled to the first input, a first output node, the second input, and a second output node, a first diode coupled to the first NMOS pair and the first output node, a second diode coupled to the first NMOS pair and the second output node, and a cascaded current source coupled to the first NMOS pair and the second NMOS pair.

According to an embodiment, an active inductor has a first conductivity type MOS transistor with a source that is connected to an electrical power source supply line and a drain that is connected to an output terminal. It has a capacitance between a gate of the first conductivity type MOS transistor and the electrical power source supply line. It has a diode element that is connected between a drain and a gate of the first conductivity type transistor. It has an electric current source that supplies a bias electric current in a forward direction to the diode element.

A transimpedance amplifier circuit includes a feedback control loop that generates a compensation current at an input of a transimpedance amplifier. The feedback control loop includes a differential integrator with an integration capacitor. A time constant associated with charging the integration capacitor is variable as a function of a pre-charge control signal. During a pre-charge phase, the pre-charge control signal is set to a first value so as to set the time constant associated with charging the integration capacitor to a first time constant value. During an operation phase, the pre-charge control signal is set to a second value so as to increase the time constant associated with charging the integration capacitor to a second time constant value greater than the first time constant value for the pre-charge phase.

An amplifier that amplifies a differential signal includes first and second input terminals for receiving two input signals; first and second diodes each including anode and cathode, the anodes being electrically connected to the first and second input terminals; first and second bias current sources being respectively electrically connected to the cathodes of the first and second diodes; an operational amplifier connected to the cathode of the first diode and the cathode of the second diode and configured to amplify a differential signal between signals generated at the cathodes of the first and second diodes; a capacitive element being electrically connected between an input and an output of the operational amplifier; and a differential amplifier provided between the operational amplifier and the first and second input terminals and configured to amplify the two input signals. The first and second bias current sources include a current mirror circuit.