Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage V.sub.OFFSET as a function of load current to substantially cancel out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use V.sub.OFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage V.sub.OUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V.sub.OUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

A differential amplifier includes first and second MOS transistors of a first conductivity type which constitute a differential input circuit, a bias current source which supplies a bias current to the first and second MOS transistors, and a third MOS transistor of the first conductivity type provided between the bias current source and the first and second MOS transistors and constituted to limit a back-gate voltage of the first and second MOS transistors.

A current-bootstrap comparator includes a receiving unit, a first current generation unit and a second current generation unit. The receiving unit receives a load voltage signal, a low threshold voltage and a high threshold voltage. The first current generation unit generates a first current. The second current generation unit generates a second current having a magnitude substantially same as a magnitude of the first current and a direction reverse to the first current. The first current and the second current are supplied to a next-stage circuit as a source current and a corresponding sink current, respectively, when the level of the load voltage signal is higher than the high threshold voltage or lower than the low threshold voltage. The magnitudes of the first current and the second current substantially equal zero when the level of the load voltage signal is between the high threshold voltage and the low threshold voltage.

Described herein is a fully-differential preamplifier comprising an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode compared to when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprise positive and negative inputs of the fully-differential preamplifier. Nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier.

A fully differential amplifier includes: an input stage comprising a first amplification circuit and a second amplification circuit, one of which is configured to generate a push signal and the other of which is configured to generate a pull signal, each by amplifying a differential input signal; an output stage for generating a differential output signal based on the push signal and the pull signal; and a feedback circuit for providing common mode feedback to the first amplification circuit based on the differential output signal, wherein the second amplification circuit may include a passive network for setting a common mode voltage of the push signal or the pull signal.

Disclosed herein is a method including sinking current from a pair of input transistors of a differential amplifier while sourcing more current to the pair of input transistors than is sunk. The method further includes generating a pair of input differential signals using a pair of input voltage regulators, and amplifying a difference between the pair of input differential signals to produce a pair of differential output voltages, using the differential amplifier. The method also includes amplifying the pair of differential output voltages using at least one voltage gain amplifier, and generating control signals for current sources that source the current to the pair of input transistors of the differential amplifier, from the pair of differential output voltages after at least amplification.

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage V.sub.OFFSET as a function of load current to substantially cancel out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use V.sub.OFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage V.sub.OUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V.sub.OUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.

Described herein is a fully-differential preamplifier comprising an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode compared to when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprise positive and negative inputs of the fully-differential preamplifier. Nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier.

A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage V.sub.OFFSET as a function of load current to substantially cancel out variations in V.sub.OUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use V.sub.OFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage V.sub.OUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V.sub.OUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.