Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.

In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.

The invention relates to an electrical circuit in the form of a transimpedance amplifier stage, and to a method for operating this circuit. The invention furthermore relates to a circuit containing at least one signal amplifier that has at least one output connection, at least one input connection or at least one pair of differential input connections and at least two voltage supply connections, one of which may also be an earth or ground connection, wherein the signal amplifier has at least one additional connection that is connected internally to at least one of the input connections or the input connection via at least one further component, for example a diode.

A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

A differential to single-ended buffer amplifier with a swing suppression resistor in the differential amplification architecture is shown. The differential to single-ended buffer amplifier has a positive input terminal, a negative input terminal, a differential to single-ended operational amplifier (DISO op amp), and a swing suppression resistor. The DISO op amp has a non-inverting input terminal and an inverting input terminal respectively coupled to the positive input terminal and the negative input terminal, and it has a single-ended output terminal that outputs the output signal of the differential to single-ended buffer amplifier. The swing suppression resistor is connected between the negative input terminal of the differential to single-ended buffer amplifier and the non-inverting input terminal of the DISO op amp.

A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.

Provided are a semiconductor device and a sensor system capable of achieving improvement of noise resistance. Thus, an output circuit 106a in the semiconductor device includes: input terminals 207n, 207p; and an output terminal 208; an output amplifier 201 connecting the input terminals 207n, 207p to the output terminal 208; a feedback element 203 returning the output terminal 208 to the input terminal 207n; a switching transistor 204; and a resistance element 206. A drain of the switching transistor 204 is connected to the input terminal 207n. The resistance element 206 is provided between a back gate of the switching transistor 204 and a power source Vdd and has impedance of a predetermined value or more for suppressing noise of a predetermined frequency generated at the input terminal 207n.

A calibration amplifier includes: a plurality of transistors and a variable resistor configured to change in response to clock pulses. During a calibration cycle, one of the plurality of transistors switches on in each calibration step based on a plurality of enable signals, and a gain of the calibration amplifier changes until an output voltage of the calibration amplifier exceeds a reference voltage and is set to a calibrated gain. The calibration amplifier outputs the output voltage by amplifying an input voltage using the calibrated gain.

In one embodiment, an apparatus comprising a first resistor, the first resistor comprising a first type of resistor having a plurality of metal wires in respective layers, the plurality of metal wires arranged in series via a plurality of vias.

A differential amplifier comprises: a long tailed pair transistor configuration comprising a differential pair of transistors and a tail transistor; and a replica circuit configured to vary a feedback current in the replica circuit to match a replica voltage to a reference voltage, wherein varying the feedback current in the replica circuit 4 provides a bias voltage to the tail transistor in the long tailed pair which controls a tail current through the tail transistor to determine a common mode voltage in the long tailed pair.