An amplifier includes a first differential input pair of transistors having a first input terminal, a second input terminal, a first output terminal, and a second output terminal. A second differential input pair of transistors has a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal. The first input terminal is coupled to the third input terminal, the second input terminal is coupled to the fourth input terminal, the first output terminal is coupled to the third output terminal, and the second output terminal is coupled to the fourth output terminal. A cross-over circuit has a control input coupled to the second fourth input terminals. The cross-over circuit is configured to vary an amount of bias current through the second differential input pair of transistors based on a magnitude of a voltage on the second and fourth input terminals.

Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.

Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.

A HDR CTIA pixel which provides automatic gain selection, and spatial and temporal coherence. The pixel comprises an input node for connection to a photocurrent, and an output node. The pixel includes a CTIA which comprises a high gain integration capacitor and a first reset switch connected between the input and output nodes, a low gain integration capacitor connected between the input node and a first node, a second reset switch connected between the first node and the output node, and a first FET connected across the second reset switch. In operation, the first FET is off during the reset phase, and is conditionally turned on during or after the integration phase. The CTIA also includes an amplifier having an inverting input connected to the input node and an output connected to the output node. The pixel can be operated in static low-gain control and dynamic low-gain control modes.

A differential power amplifier having first and second amplifiers with first and second signal output terminals along with bias circuitry in communication with the first and second amplifiers is disclosed. The differential amplifier further includes a first output clamp coupled to the first signal output terminal and a bias control terminal of the bias circuitry, wherein the first output clamp is configured to limit voltage at the first signal output terminal to a first predetermined voltage magnitude and lower bias current to the first amplifier in response to an overvoltage at the first signal output terminal. A second output clamp is coupled to the second signal output terminal and is configured to limit voltage at the second signal output terminal to a second predetermined voltage magnitude.

A differential power amplifier having first and second amplifiers with first and second signal output terminals along with bias circuitry in communication with the first and second amplifiers is disclosed. The differential amplifier further includes a first output clamp coupled to the first signal output terminal and a bias control terminal of the bias circuitry, wherein the first output clamp is configured to limit voltage at the first signal output terminal to a first predetermined voltage magnitude and lower bias current to the first amplifier in response to an overvoltage at the first signal output terminal. A second output clamp is coupled to the second signal output terminal and is configured to limit voltage at the second signal output terminal to a second predetermined voltage magnitude.

An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.

A HDR CTIA pixel which provides automatic gain selection, and spatial and temporal coherence. The pixel comprises an input node for connection to a photocurrent, and an output node. The pixel includes a CTIA which comprises a high gain integration capacitor and a first reset switch connected between the input and output nodes, a low gain integration capacitor connected between the input node and a first node, a second reset switch connected between the first node and the output node, and a first FET connected across the second reset switch. In operation, the first FET is off during the reset phase, and is conditionally turned on during or after the integration phase. The CTIA also includes an amplifier having an inverting input connected to the input node and an output connected to the output node. The pixel can be operated in static low-gain control and dynamic low-gain control modes.

Techniques for limiting the output voltage of an amplifier without directly affecting an output current of the amplifier are provided. In an example, an amplifier can include a plurality of amplifier stages configured to receive an input voltage and to provide an output voltage as a function of the input voltage, and a comparator configured to receive a voltage limit and a representation of the output voltage of the amplifier, to adjust current at an input to a first amplifier stage of the plurality of amplifier stages when the output voltage violates the voltage limit, and to clamp the output voltage at an offset from the voltage limit.

An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.