An amplifier circuit includes a resistor divider (R.sub.REF) comprising n resistive elements, two main nodes defined at each end thereof, two readout nodes (d.sub.1, d.sub.2), resistor nodes (q) defined between adjacent resistive elements, and an input current source (I.sub.REF) connected or connectable to the first main node (a). The resistor divider (R.sub.REF) comprises two arrays of addressable switch elements controllable by a feedback signal (s.sub.FB) to be open or closed. The amplifier circuit includes a differential pair of transistors (T.sub.1, T.sub.2), wherein source terminals of each of the transistors (T.sub.1, T.sub.2) are connected to the second node (b), gate terminals of the transistors (T.sub.1, T.sub.2) are connected to input signals (v.sub.1, v.sub.2), drain terminals of the transistors (T.sub.1, T.sub.2) are connected to current sources (I.sub.1, I.sub.2), and bulk terminals of the transistors (T.sub.1, T.sub.2) are connected to the readout nodes (d.sub.1, d.sub.2). The amplifier circuit functions as a difference amplifier, wherein the bulk terminals affect a threshold of the respective transistors (T.sub.1, T.sub.2) so as to add or subtract a differential signal derived from the readout nodes (d.sub.1, d.sub.2) of the resistor divider (R.sub.REF) determined by the feedback signal (s.sub.FB).

Certain aspects of the present disclosure generally relate to using cross-coupled transistors for source degeneration of an amplification stage. For example, the amplification stage generally includes a differential amplifier comprising transistors, cross-coupled transistors coupled to the differential amplifier, and an impedance coupled between drains of the cross-coupled transistors. In certain aspects, the differential amplifier comprises a push-pull amplifier, and the transistors of the push-pull amplifier comprise cascode-connected transistors.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.

An amplifier circuit includes a voltage-to-current conversion circuit and a current-to-voltage conversion circuit. The voltage-to-current conversion circuit generates a current signal according to an input voltage signal, and includes an operational transconductance amplifier (OTA) used to output the current signal at an output port of the OTA. The current-to-voltage conversion circuit generates an output voltage signal according to the current signal, and includes a linear amplifier (LA), wherein an input port of the LA is coupled to the output port of the OTA, and the output voltage signal is derived from an output signal at an output port of the LA.

Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes an input port, an output port, a first differential transistor pair coupled to the input port and the output port and a second differential transistor pair. The CTLE circuit further includes a first degenerative impedance circuit coupled between the first differential transistor pair and ground. The first degenerative impedance includes switchable components to vary impedance of the first degenerative impedance circuit. The CTLE circuit also includes a second degenerative impedance circuit coupled between the second differential transistor pair and ground. The second degenerative impedance includes switchable components to vary impedance of the second degenerative impedance circuit, wherein the resistive part of the impedance of the first degenerative impedance circuit is equal to the impedance of the second degenerative impedance circuit.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

An amplifier includes first and second input transistors, a first current mirror, a second current mirror, and a third current mirror. An input terminal of the first current mirror is coupled to a drain of the first input transistor, an input terminal of the second current mirror is coupled to a drain of the second input transistor, and an input terminal of the third current mirror is coupled to an output terminal of the first current mirror. An output terminal of the first current mirror and an output terminal of the third current mirror are coupled to an output of the amplifier. The amplifier also includes third and fourth input transistors, wherein a drain of the third input transistor is coupled to the input terminal of the third current mirror, and a drain of the fourth input transistor is coupled to the output of the amplifier.