An internal voltage offset between a positive input and a negative input of a first operational amplifier is compensated. The negative input and the positive input of the first operational amplifier are coupled at the same voltage level. A comparison current generated at an output of the first operational amplifier has a sign that is representative of a sign of the internal voltage offset. The output of the first operational amplifier is biased to a threshold voltage using a current-to-voltage converter. A control voltage is generated from a sum of the threshold voltage and a voltage conversion of the comparison current. Compensation for the internal voltage offset between the positive and negative inputs of the first operational amplifier is made dependent on the control voltage.

A controlled active resistance. The active resistance is implemented on an integrated circuit. In some embodiments, the active resistance includes a MOSFET. In alternate embodiments, the active resistance includes a MOSFET and a resistor. The control for the active resistance includes a reference resistor and an operational amplifier. The control for the active resistance further includes two current sources: i) a current source producing a current that is proportional to absolute temperature, and ii) another current source that is produced by a bandgap voltage reference. In one aspect, the active resistance generates an effective resistance that is proportional to thermal voltage. In another aspect, the active resistance generates an effective resistance that is proportional to inverse of the thermal voltage. In an alternate aspect, the current sources have various dependencies, and the active resistance generates an effective resistance that is proportional to those dependencies.

A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.

A controlled active resistance. The active resistance is implemented on an integrated circuit. In some embodiments, the active resistance includes a MOSFET. In alternate embodiments, the active resistance includes a MOSFET and a resistor. The control for the active resistance includes a reference resistor and an operational amplifier. The control for the active resistance further includes two current sources: i) a current source producing a current that is proportional to absolute temperature, and ii) another current source that is produced by a bandgap voltage reference. In one aspect, the active resistance generates an effective resistance that is proportional to thermal voltage. In another aspect, the active resistance generates an effective resistance that is proportional to inverse of the thermal voltage. In an alternate aspect, the current sources have various dependencies, and the active resistance generates an effective resistance that is proportional to those dependencies.

Briefly, embodiments of claimed subject matter relate to determination of a high-impedance state or a low-impedance state of a resistive memory element over a wide range of temperature, such as temperatures approaching 40.0 C. to temperatures approaching +125.0 C. Such determination may be brought about by implementing a circuit which, according to various embodiments described herein, emulates a reference impedance having a negative temperature coefficient.

Briefly, embodiments of claimed subject matter relate to determination of a high-impedance state or a low-impedance state of a resistive memory element over a wide range of temperature, such as temperatures approaching 40.0 C. to temperatures approaching +125.0 C. Such determination may be brought about by implementing a circuit which, according to various embodiments described herein, emulates a reference impedance having a negative temperature coefficient.

A pseudo-resistor structure, comprises: a first and a second PMOS transistor or PN diode configured as two-terminal devices, wherein the positive terminal of the first PMOS transistor or PN diode is connected to the positive terminal of the second PMOS transistor or PN diode, and wherein the negative terminal of the first PMOS transistor or PN diode is connected to an input (A) of the pseudo-resistor structure and wherein the negative terminal of the second PMOS transistor or PN diode is connected to an output (C) of the pseudo-resistor structure, and a dummy transistor or dummy diode connected to the input (A), wherein the dummy transistor or dummy diode is further connected to a bias voltage for compensating a leakage current through the first and the second PMOS transistors or PN diodes. A closed-loop operational amplifier circuit comprising the pseudo-resistor structure is provided. Also, a bio-potential sensor comprising the closed-loop operational amplifier circuit is provided.

An amplifier circuit with a high pass filter is constructed to include an operational amplifier (op amp) with a feedback loop in which a capacitor is in parallel with a field effect transistor (FET) configured as a gate tunneling resistor. To configure as a gate tunneling resistor, the source and drain of the FET are tied together, and large resistance is provided through the thin oxide layer between the gate and the source/drain. A bias voltage to the FET can be provided through a separate FET, also configured as a gate tunneling resistor. Additional gate tunneling FETs, also in parallel with the capacitor, can be switched into the circuit in order to provide different resistances, and thus different corner frequencies of the filter. Bias voltages may be supplied by one or more gate tunneling FETs. A fully differential op amp can have complementary feedback loops from its differential outputs, each feedback loop employing one or more gate tunneling FETs.