A current sensing circuit includes a filtering circuit, an amplifier, a first resistor, a first transistor and a second transistor. The filtering circuit is coupled to two terminals of a sensing resistor. The amplifier has a first input terminal, a second input terminal and an output terminal. The second input terminal is coupled to the filtering circuit. The first resistor is coupled between the filtering circuit and the first input terminal of amplifier. A control terminal of the first transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the first input terminal of amplifier and its second terminal is grounded through a second resistor. A control terminal of the second transistor is coupled to the output terminal of amplifier, and its first terminal is coupled to the second input terminal of amplifier and its second terminal is grounded through a third resistor.

An instrumentation amplifier that includes input capacitance cancellation is provided. The architecture includes programmable capacitors between the input stage and a current feedback loop of the instrumentation amplifier to cancel input capacitances from electrode cables and a printed circuit board at the front end. An on-chip calibration unit can be employed to calibrate the programmable capacitors and improve the input impedance.

An operational amplifier comprises: a first amplifier stage 4 comprising a first differential pair of transistors 8, 10 arranged to receive and amplify a differential input signal 18, 20 thereby providing a first differential output signal 22, 24; and a second amplifier stage 6 comprising a second differential pair of transistors 26, 28 arranged to receive and amplify the first differential output signal 22, 24 thereby providing a second differential output signal 38, 40.

In at least one embodiment, a method for operating a receiver includes configuring a receiver front-end circuit of the receiver according to a selected power consumption configuration. The method includes adjusting a quiescent current of a programmable flat gain stage coupled to the receiver front-end circuit according to the selected power consumption configuration to compensate for any gain loss of the receiver front-end circuit in the selected power consumption configuration. The selected power consumption configuration may be a reduced power consumption configuration and the programmable flat gain stage may be configured to at least partially compensate for the gain loss of the receiver front-end circuit in the reduced power consumption configuration.

A receiver front-end includes a first peaking gain stage configured to amplify a received differential pair of signals received on an input differential pair of nodes. The first peaking gain stage has a first frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency. A second peaking gain stage is configured to amplify a differential pair of signals generated by the first peaking gain stage. The second peaking gain stage has a high input impedance and a second frequency response including a second peak gain at or near the carrier frequency in a second pass band. The second peak gain occurs just prior to a second cutoff frequency. The first peaking gain stage and the second peaking gain stage have a cascaded peak gain at or near the carrier frequency.

A shaper circuit includes a first amplifier including an input and an output, the input being configured to receive an input signal, which includes one or more current pulses, a feedback component coupled to the output and to the input of the first amplifier thereby forming a feedback loop of the first amplifier, and an RC component coupled to the output of the first amplifier and to a reference potential terminal. Therein the shaper circuit is configured to provide an output signal as a function of the input signal, the output signal including one or more voltage pulses, and the RC component is configured to largely cancel a low frequency pole of the feedback loop of the first amplifier.

A receiver front-end includes a first peaking gain stage configured to amplify a received differential pair of signals received on an input differential pair of nodes. The first peaking gain stage has a first frequency response including a first peak gain at or near a carrier frequency in a first pass band. The first peak gain occurs just prior to a first cutoff frequency. A second peaking gain stage is configured to amplify a differential pair of signals generated by the first peaking gain stage. The second peaking gain stage has a high input impedance and a second frequency response including a second peak gain at or near the carrier frequency in a second pass band. The second peak gain occurs just prior to a second cutoff frequency. The first peaking gain stage and the second peaking gain stage have a cascaded peak gain at or near the carrier frequency.

A high-efficiency high-integrated receiver is provided. The radar receiver according to an embodiment of the present disclosure includes a receiver configured to receive a radar signal, a processor configured to attenuate a magnitude of a low frequency band of the received signal of the receiver, a filter configured to perform a low pass filtering on an output signal of the processor, and an ADC configured to A/D convert the output signal of the filter. Accordingly, it is possible to demodulate all the signals being reflected from targets in various distances when even using a low resolution ADC, thereby reducing the manufacturing cost and power consumption.

An operational amplifier comprises: a first amplifier stage 4 comprising a first differential pair of transistors 8, 10 arranged to receive and amplify a differential input signal 18, 20 thereby providing a first differential output signal 22, 24; and a second amplifier stage 6 comprising a second differential pair of transistors 26, 28 arranged to receive and amplify the first differential output signal 22, 24 thereby providing a second differential output signal 38, 40.

A high-efficiency high-integrated receiver is provided. The radar receiver according to an embodiment of the present disclosure includes a receiver configured to receive a radar signal, a processor configured to attenuate a magnitude of a low frequency band of the received signal of the receiver, a filter configured to perform a low pass filtering on an output signal of the processor, and an ADC configured to A/D convert the output signal of the filter. Accordingly, it is possible to demodulate all the signals being reflected from targets in various distances when even using a low resolution ADC, thereby reducing the manufacturing cost and power consumption.