An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

An amplifier and a method of outputting a waveform of a music signal capable of outputting a waveform of a music signal exceeding a power supply voltage is provided. An amplifier includes a power supply, an input terminal for a music signal, an amplifying circuit which amplifies the music signal using the power supply, and a jumping-up circuit which is connected to an output end of the amplifying circuit and outputs a waveform exceeding a voltage value of the power supply.

A front-end amplifier circuit for receiving a biological signal includes a signal channel. The signal channel amplifies the biological signal to generate a detection current and includes a capacitive-coupled transconductance amplifier. The capacitive-coupled transconductance amplifier amplifies the biological signal with a transconductance gain to generate a first current.

A voltage clamping circuit is provided. In an embodiment, the voltage clamping circuit includes a plurality of gain shifting circuits and a signal processing circuit. The plurality of gain shifting circuits receive an input voltage and voltage levels to generate a plurality of shifted voltages. The signal processing circuit generates a difference value of the plurality of shifted voltages to generate an output voltage according to the difference value, such that the voltage clamping circuit achieves an implementation of a passing band or a rejection of the input voltage.

A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ⅔ of the data rate.

A shaper circuit includes a first amplifier including an input and an output, the input being configured to receive an input signal, which includes one or more current pulses, a feedback component coupled to the output and to the input of the first amplifier thereby forming a feedback loop of the first amplifier, and an RC component coupled to the output of the first amplifier and to a reference potential terminal. Therein the shaper circuit is configured to provide an output signal as a function of the input signal, the output signal including one or more voltage pulses, and the RC component is configured to largely cancel a low frequency pole of the feedback loop of the first amplifier.

A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ⅔ of the data rate.

Amplifiers can be found in pipelined ADCs and pipelined-SAR ADCs as inter-stage amplifiers. The amplifiers can in some cases implement and provide gains in high speed track and hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and samplers of high speed ADCs. The amplifiers can be employed without resetting, and with incomplete settling, to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.

An amplifier includes a first input circuit, a second input circuit, a first compensation circuit, a second compensation circuit. The first input circuit changes a voltage level of the negative output node based on a first input signal. The second input circuit changes a voltage level of the positive output node based on a second input signal. The first compensation circuit changes the voltage level of the positive output node based on the first input signal. The second compensation circuit changes the voltage level of the negative output node based on the second output signal.

An example apparatus includes: a first voltage source, a first amplifier having a noninverting input adapted to be coupled to a photodiode anode and coupled to the first voltage source, an inverting input adapted to be coupled to a photodiode cathode, and an output, a first resistor coupled to the first amplifier inverting input and to the first amplifier output, a first capacitor coupled to the inverting input of the first amplifier and the first amplifier output, and a second voltage source different from the first voltage source. There is a second amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to the output of the first amplifier, the inverting input is coupled to the second voltage source, and there is a second resistor coupled to the inverting input and the output of the second amplifier.