A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

A radio-frequency circuit is provided that includes a power amplifier, a control circuit, an on-off switch, a connection terminal, and a mount board. The power amplifier supports an APT system and an ET system. The control circuit controls the power amplifier by using the APT system and the ET system. The on-off switch is connected in series to a capacitive element connected between a path and the ground. The connection terminal is connected to the capacitive element. Moreover, the control circuit overlies the connection terminal in plan view in the thickness direction of the mount board.

A semiconductor device is provided. The semiconductor device comprises an output terminal from which an output voltage is output, a switching converter configured to control the output voltage on the basis of a first reference voltage, a load capacitor configured to be charged with a voltage corresponding to the output voltage, a linear amplifier connected to one end of an alternating current (AC) coupling capacitor and configured to control a voltage of the AC coupling capacitor on the basis of a second reference voltage, and a switching circuit configured to control a charging speed of the load capacitor and control a connection between the output terminal and one end and another end of the AC coupling capacitor.

Various embodiments of the disclosure relate to a device and a method for supplying power to a plurality of power amplifiers in an electronic device. An electronic device may include: a first power amplifier, a second power amplifier, a third power amplifier, a first power supply module including a power supply configured to supply power to the first power amplifier or the second power amplifier, a second power supply module including a power supply configured to supply power to the second power amplifier or the third power amplifier, and a detection module comprising circuitry configured to identify a state of a connection between the second power amplifier and the first power supply module and a state of a connection between the second power amplifier and the second power supply module, wherein the detection module may be configured to output a power control signal based on detecting that the second power amplifier is connected to the first power supply module and the second power supply module, wherein power supply to the second power amplifier from the first power supply module or the second power supply module may be shut off based on the power control signal of the detection module.

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

A power amplifier has an amplifier cell with an input terminal receiving an input signal and an output terminal providing an output signal. A bias network is coupled to the output terminal of the amplifier cell to provide a bias signal to the amplifier cell. A shutdown circuit is coupled to the bias network to disable the bias network in response to the input signal. The shutdown circuit has a transistor with a first conduction terminal coupled to the bias network, a second conduction terminal coupled to a power supply terminal. The shutdown circuit further has a first resistor with a first terminal coupled to the input terminal, and a second resistor with a first terminal coupled to a second terminal of the first resistor at a node, and a second terminal coupled to the power supply terminal. The control terminal of the transistor is coupled to the node.

A semiconductor device includes a differential amplification circuit that outputs differential output signals Vo1 and Vo2, external output terminals PD1 and PD2 to which one of the differential output signals Vo1 and Vo2 and single end signals Vo3 and Vo4 is selectively supplied, switch units SW1 and SW2 that control a conduction state between the external output terminal PD1 and the feedback line and a conduction state between the external output terminal PD2 and the feedback line, respectively, resistance elements R1 and R2 respectively provided in series with the switch units SW1 and SW2, a CMFB circuit that controls a common mode voltage of the differential amplification circuit according to a difference between an intermediate voltage Vcm of the external output terminals PD1 and PD2 in the feedback line and a reference voltage Vref, and a switch unit SW3 that controls to supply a clamp voltage to the feedback line.

Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.

A method of operating a power amplifier supplying power to an antenna, supplying switched power to the power amplifier comprises in a first mode of operation via a driver circuit and one or more switches to switch the supply of power to the power amplifier on and off periodically; and calibrating the power amplifier in a second mode of operation. The calibrating comprises supplying voltage to the power amplifier via the same driver circuit and one or more switches for a calibration pulse duration longer than the on/off period. A power supply and an RF front end comprising the power supply are also disclosed.

An amplifying circuit includes a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit. The amplifying circuit also includes a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit.