Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry implementing a low noise amplifier (LNA) with phase-shifting circuitry to achieve a continuous phase at the output of the LNA. One aspect is an amplifier including a high gain active path comprising active circuitry, and a low gain path comprising passive circuitry and phase-shifting circuitry. In one or more aspects, the phase-shifting circuitry is configured to shift a phase of an input signal within the low gain path such that the phase of an output signal outputted from the low gain path approximately matches a phase of an output signal outputted from the high gain active path. In at least one aspect, a gain of the high gain active path is higher than a gain of the low gain passive path.

An amplifier may include multiple stages, with the multiple stages arranged in a fan-out configuration. The fan-out configuration provides multiple amplified signals at multiple amplifier output nodes, which may be coupled to a shared set of downconverters. The shared downconverters may support processing of only a smaller bandwidth than the largest possible bandwidth of an input RF signal input to the amplifier. For example, the downconverters may support a bandwidth matching a smallest bandwidth of a supported RF signal. For example, when the amplifier is intended to support 5G mmWave RF signals and 5G sub-6 GHz RF signals, the downconverters may each individually support a bandwidth of carriers in the 5G sub-6 GHz RF signals but not individually support the entire bandwidth of a possible 5G mmWave RF signal.

An amplifier circuit includes an amplifier for generating an amplified input signal according to an input signal, and an attenuator circuit coupled to the amplifier. The attenuator circuit includes an input terminal for receiving the input signal or the amplified input signal, an output terminal, a reference voltage terminal, a zeroth resistor-switch circuit, a first resistor-switch circuit, and a second resistor-switch circuit. The zeroth resistor-switch circuit includes a first terminal coupled to the input terminal, a second terminal coupled to the output terminal, a zeroth switch coupled to the first terminal of the zeroth resistor-switch circuit and the second terminal of the zeroth resistor-switch circuit, a zeroth resistor coupled between the first terminal of the zeroth resistor-switch circuit and the second terminal of the zeroth resistor-switch circuit, a first resistor coupled between the zeroth resistor and the second terminal of the zeroth resistor-switch circuit, and a first switch.

An amplification circuit includes a first switching circuit that includes input terminals and first and second output terminals and that puts the second output terminal into an open state with respect to the input terminals while selectively putting the first output terminal into a state of being connected to any of the input terminals or selectively puts the second output terminal into a state of being connected to any of input terminals while putting the first output terminal into a state of being open with respect to the input terminals; a matching network that is connected to the first output terminal; an amplifier that is connected to an output side of the matching network; a second switching circuit that is connected to an output side of the amplifier; and a bypass path that electrically connects the second output terminal and an output terminal of the second switching circuit. The amplifier is a variable-gain amplifier.

An RF matrix switch has a first set of card slots at selected locations on the chassis and a second set of card slots at different selected locations on the chassis as well as input cards and output cards. The input cards, the output cards, the first set of card slots and the second set of card slots are all configured so that the input cards and the output cards fit into all of these slots. Reroute cards can be provided for any unused card slots. The RF matrix switch also may have an active power management system in which there is a power control switch connected to each amplifier that turns the amplifier off when the amplifier is not being used.

An active circuit includes an active element, an input unit, and a bypass unit. The active element is coupled to an output terminal of the active circuit for outputting an output signal. The input unit is coupled to an input terminal of the active circuit, and is coupled to an input terminal of the active element through a node. The input unit adjusts a capacitance value of the input unit according to a first control signal. The bypass unit is coupled to an output terminal of the input unit through the node, and is coupled to the output terminal of the active circuit. The bypass unit turns on or off a signal bypassing path according to a second control signal.

Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.

Amplifiers with wide input range and low input capacitance are provided. In certain embodiments, an amplifier input stage includes a pair of input terminals, a pair of n-type input transistors, a first pair of isolation switches connected between the input terminals and the n-type input transistors, a pair of p-type input transistors, and a second pair of isolation switches connected between the input terminals and the p-type input transistors. The amplifier input stage further includes a control circuit that determines whether to use the n-type input transistors and/or the p-type input transistors for amplification based on a detected common-mode voltage of the input terminals. The control circuit opens the first pair of isolation switches to decouple the input terminals from the n-type input transistors when unused, and opens the second pair of isolation switches to decouple the input terminals from the p-type input transistors when unused.

Techniques for providing low-cost and effective jammer rejection for an amplifier is disclosed. The amplifier includes an input node and an output node, a first transistor and a second transistor, a load circuitry, an inductor, and a capacitor. A first terminal of the first transistor is coupled to a ground. A second terminal of the first transistor is coupled to a first terminal of the second transistor. A second terminal of the second transistor is coupled to the output node. The load circuitry is coupled between a power supply and the second terminal of the second transistor. A first terminal of the inductor is coupled to the ground through a first switch. A first terminal of the capacitor is coupled to the first terminal of the second transistor and a second terminal of the capacitor is coupled to a second terminal of the inductor.

A variable gain low noise amplifier (LNA) and a method for controlling a gain of the variable gain LNA are provided. The variable gain LNA may include a first transistor, a first degeneration inductor, a second transistor and a second degeneration inductor, wherein the first degeneration inductor is coupled to a source terminal of the first transistor, and the second degeneration inductor is coupled to a source terminal of the second transistor. Gate terminals of the first transistor and the second transistor are configured to receive an input signal. The first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA. More particularly, a gain of the variable gain LNA is determined by controlling whether to turn off the second branch.