A multi-stage amplifier circuit includes: a front stage amplification circuit, for generating a front stage amplification signal according to a difference between a primary reference signal and a primary feedback signal; an output adjustment circuit, for generating a driving signal according to the front stage amplification signal; and an output transistor, controlled by the driving signal to generate an output signal. The output adjustment circuit includes: an adjustment transistor biased by a differential current of the front stage amplification signal; and an impedance adjustment device biased by the differential current. A resistance of the impedance adjustment device is determined by a difference between an adjustment feedback signal and an adjustment reference signal. The driving signal is determined by a product of a resistance of the impedance adjustment device multiplied by the differential current of the front stage amplification signal, and a drain-source voltage of the adjustment transistor.

A multi-stage amplifier circuit includes: a front stage amplification circuit, for generating a front stage amplification signal according to a difference between a primary reference signal and a primary feedback signal; an output adjustment circuit, for generating a driving signal according to the front stage amplification signal; and an output transistor, controlled by the driving signal to generate an output signal. The output adjustment circuit includes: an adjustment transistor biased by a differential current of the front stage amplification signal; and an impedance adjustment device biased by the differential current. A resistance of the impedance adjustment device is determined by a difference between an adjustment feedback signal and an adjustment reference signal. The driving signal is determined by a product of a resistance of the impedance adjustment device multiplied by the differential current of the front stage amplification signal, and a drain-source voltage of the adjustment transistor.

Amplifiers, amplification circuits, and phase shifters, for example, for flexibly adjusting an output phase to thereby meet a requirement of a constant phase on a link in a communications field, are provided. In one aspect, an amplifier includes first, second, and third MOS transistors. The first MOS transistor includes a gate separately coupled to a signal input end and a bias voltage input end, a source coupled to a power supply, and a drain separately coupled to sources of the second and third MOS transistors. A drain of the third MOS transistor is coupled to a ground, and a drain of the second MOS transistor is coupled to a signal output end. The bias voltage input end is configured to receive a bias voltage to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end.

Provided is an amplification circuit that includes: a low-noise amplifier that includes an FET as an amplification element and that amplifies a radio-frequency signal inputted to the gate of the FET; an input matching network that matches the input impedance of the low-noise amplifier; and a switch that is serially connected between ground and a node on a line connecting the input matching network and the gate of the FET to each other.

Provided is an amplifier that includes a first transistor including a gate terminal to which an applied input signal is input, where a current depending on the applied input signal flows through the first transistor. A gate terminal of a second transistor is connected to a load section, and a current depending on a change in a voltage of the drain terminal of the first transistor flows through the second transistor. A source terminal of the first transistor and a drain terminal of the second transistor are connected in common to a first resistance, and the current from the first transistor and the current from the second transistor flow through the first resistance. A third transistor supplies a current approximately equal to the current of the second transistor. The current supplied by the third transistor is output from an output end.

A signal to be amplified is applied to a gate terminal of an amplifier element that amplifies the signal and that is a transistor, the bias circuit includes: a switching element having a first terminal and a second terminal, the first terminal being electrically connected to the gate terminal; and a trap compensation element having a third terminal and a fourth terminal, the third terminal being connected to the second terminal. Further, the bias circuit includes a control circuit to apply a bias voltage to the gate terminal. Further, the bias circuit includes a voltage application circuit to apply a first voltage to the fourth terminal when the signal to be amplified is a transmission signal, and apply a second voltage to the fourth terminal when the signal to be amplified is a reception signal, the second voltage being a negative voltage.

A signal to be amplified is applied to a gate terminal of an amplifier element that amplifies the signal and that is a transistor, the bias circuit includes: a switching element having a first terminal and a second terminal, the first terminal being electrically connected to the gate terminal; and a trap compensation element having a third terminal and a fourth terminal, the third terminal being connected to the second terminal. Further, the bias circuit includes a control circuit to apply a bias voltage to the gate terminal. Further, the bias circuit includes a voltage application circuit to apply a first voltage to the fourth terminal when the signal to be amplified is a transmission signal, and apply a second voltage to the fourth terminal when the signal to be amplified is a reception signal, the second voltage being a negative voltage.

A charge sensor element includes a charge collecting detector configured to generate an intensity signal indicative of an amount of charge at an internal charge sensor element node, an amplifier transistor that is electrically connected to the internal charge sensor element node and configured to amplify the intensity signal, and a reset transistor that is electrically connected to the internal charge sensor element node and configured to reset the intensity signal. The amplifier transistor or the reset transistor includes a front gate and a back gate that are configured to control the amplifier transistor or the reset transistor.

A charge sensor element includes a charge collecting detector configured to generate an intensity signal indicative of an amount of charge at an internal charge sensor element node, an amplifier transistor that is electrically connected to the internal charge sensor element node and configured to amplify the intensity signal, and a reset transistor that is electrically connected to the internal charge sensor element node and configured to reset the intensity signal. The amplifier transistor or the reset transistor includes a front gate and a back gate that are configured to control the amplifier transistor or the reset transistor.

A circuit for processing an N-level pulse amplitude modulation (PAM-N) signal according to an embodiment of the present invention comprises: an input unit receiving an input signal; a main amplifier connected to the input unit to amplify the input signal with a first gain; and an output unit outputting an output signal of the main amplifier, and the circuit further comprises an auxiliary amplifier connected in parallel with the main amplifier between the input unit and the output unit to variably amplify at least a portion of the input signal and apply the signal to the output unit according to a linearity improvement control signal corresponding to the output signal.