H03F3/265

Power amplifying circuits

A power amplifying circuit includes a first input terminal applied with a first bias voltage, a first amplifying circuit generating a first output signal and a second output signal according to an input signal and a first matching circuit combining the first output signal and the second output signal to generate an output signal. The first amplifying circuit includes a first transistor having a first electrode coupled to the first input terminal and a second electrode applied with a second bias voltage and a second transistor having a first electrode s coupled to the first input terminal and a second electrode applied with a third bias voltage. The first transistor generates the first output signal according to the first bias voltage and the second bias voltage. The second transistor generates the second output signal according to the first bias voltage and the third bias voltage.

CURRENT MIRROR CIRCUIT
20230050798 · 2023-02-16 · ·

The present disclosure provides an electronic circuit having one reference current terminal arranged to connect to a reference current generator, an MOS current mirror stage, an MOS push-pull amplifier stage operatively coupled to the current mirror stage and the current mode amplifier stage.

Amplifier circuitry for carrier aggregation

An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.

RECONFIGURABLE OUTPUT BALUN FOR WIDEBAND PUSH-PULL POWER AMPLIFIERS

Reconfigurable output baluns for wideband push-pull amplifiers are disclosed. In certain embodiments, a mobile device includes a transceiver that generates a first radio frequency signal of a first frequency band and a second radio frequency signal of a second frequency band, and a front-end system including a push-pull power amplifier that selectively amplifies one of the first radio frequency signal or the second radio frequency signal based on a band control signal. The push-pull power amplifier includes an input balun, an output balun, and a pair of amplifiers coupled between the input balun and the output balun. The band control signal is operable to control an impedance of the output balun.

Amplifier biasing techniques
11545936 · 2023-01-03 · ·

Techniques for biasing output transistor of a push-pull amplifier output stage are provided. In certain applications the techniques can improve efficiency of the amplifier. In an example, a circuit can include an output stage including first and second output transistors, a first scaled replica transistor corresponding to the first output transistor, and an amplifier circuit in a feedback arrangement for biasing a gate of the first output transistor at a level that, at a specified stand-by current level of the first output transistor, reproduces a voltage difference between the drain and source terminals of the first output transistor across the drain and source terminals of the first replica transistor.

PUSH-PULL RADIO FREQUENCY POWER AMPLIFIER AND METHOD FOR CONTROLLING CIRCUIT

A push-pull radio frequency power amplifier includes a coupling feedback circuit, a drive stage circuit and a power output stage circuit, in which the coupling feedback circuit is connected with the drive stage circuit and/or the power output stage circuit; the coupling feedback circuit is configured to generate an alternating voltage at an input end of a first transistor and/or an input end of a push-pull transistor; when the alternating voltage and a voltage at the input end are in a same direction, a positive feedback of an input signal at the input end is achieved; and the first transistor represents a transistor in the drive stage circuit and the push-pull transistor represents a second transistor and a third transistor that form a push-pull structure in the power output stage circuit.

Device stack with novel gate capacitor topology
11509270 · 2022-11-22 · ·

Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.

Electronic device and wireless communication system thereof

An electronic device includes a network monitor configured to acquire network environment information related to a radio frequency (RF) transmission signal; a transceiver configured to generate an envelope signal of the RF transmission signal; a transmission (Tx) module including a power amplifier for receiving the RF transmission signal from the transceiver and amplifying the RF transmission signal; and an envelope tracking (ET) modulator configured to receive the envelope signal from the transceiver and to provide a bias of a power amplifier to correspond to the envelope signal, wherein the ET modulator determines a magnitude of the bias of the power amplifier based on the network environment information acquired by the network monitor.

ELECTRONIC DEVICE AND WIRELESS COMMUNICATION SYSTEM THEREOF

An electronic device includes a network monitor configured to acquire network environment information related to a radio frequency (RF) transmission signal; a transceiver configured to generate an envelope signal of the RF transmission signal; a transmission (Tx) module including a power amplifier for receiving the RF transmission signal from the transceiver and amplifying the RF transmission signal; and an envelope tracking (ET) modulator configured to receive the envelope signal from the transceiver and to provide a bias of a power amplifier to correspond to the envelope signal, wherein the ET modulator determines a magnitude of the bias of the power amplifier based on the network environment information acquired by the network monitor.

HIGHLY EFFICIENT DUAL-DRIVE POWER AMPLIFIER FOR HIGH RELIABILITY APPLICATIONS
20230084449 · 2023-03-16 ·

A dual-drive power amplifier (PA) where the PA core includes a differential pair of transistors M1 and M2 that are driven by a coupling network having two transmission-line couplers, where a first transmission line section of a coupler is configured to transmit an input signal Vin through to drive a gate of the opposite transistor, while the second transmission line section is grounded at one end and coupled with the first transmission line section such that a coupled portion αVin of the input signal Vin drives the source terminal of a corresponding transistor. The arrangement of the coupling network allows the source terminals to be driven below ground potential. Embodiments disclosed here further provide an input matching network, a driver, an inter-stage matching network, and an output network for practical implementation of the PA core.