Disclosed are a receiver control circuit and a terminal. The receiver control circuit includes: a smart power amplifier module, a coder-decoder, and a receiver. The smart power amplifier module is electrically connected to the receiver by a first switch module. The first switch module includes a first switch component unit that is formed by a metal oxide semiconductor field-effect transistor (MOSFET). The first switch module further includes a first follower unit, where the first follower unit is configured to keep an unchanged voltage difference between a gate electrode of the MOSFET of the first switch component unit and a drain electrode thereof, and a gate electrode voltage of the MOSFET of the first switch component unit is greater than a drain electrode voltage thereof. The coder-decoder is electrically connected to the receiver by the second switch module. The second switch module includes a second switch component unit.

Disclosed are a receiver control circuit and a terminal. The receiver control circuit includes: a smart power amplifier module, a coder-decoder, and a receiver. The smart power amplifier module is electrically connected to the receiver by a first switch module. The first switch module includes a first switch component unit that is formed by a metal oxide semiconductor field-effect transistor (MOSFET). The first switch module further includes a first follower unit, where the first follower unit is configured to keep an unchanged voltage difference between a gate electrode of the MOSFET of the first switch component unit and a drain electrode thereof, and a gate electrode voltage of the MOSFET of the first switch component unit is greater than a drain electrode voltage thereof. The coder-decoder is electrically connected to the receiver by the second switch module. The second switch module includes a second switch component unit.

A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.

A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.

Achieved is a load drive device capable of suppressing local concentration of temperature at the time of absorbing a counter electromotive force of an inductive load while suppressing a size of a power transistor. The load drive device includes a first transistor connected between a first control electrode and an inductive load. Further, the load drive device includes an active clamp circuit that becomes conductive when a terminal voltage of a second control electrode between the first transistor and the inductive load exceeds a threshold. Furthermore, the load drive device includes a second transistor connected to the second control electrode and connected in parallel to the first transistor.

In one embodiment, stable and controlled circuit element biasing is provided in a circuit comprising a voltage source operable to output a first voltage, a reference voltage source operable to output a reference voltage, a circuit element biased, during operation, by the first voltage at a first end and by a second voltage at a second end, a voltage controller coupled to the second end of the circuit element, wherein the voltage controller is operable to adjust the second voltage based on a gain output, a gain controller operable to receive the reference voltage as a first input and the second voltage as a second input, wherein the gain controller is operable to generate, at an output of the gain controller, the gain output based on the second voltage and the reference voltage, and a feedback loop that extends from the output of the gain controller, through the voltage controller, and to the second input.

In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.

In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.

Variations in a receiving circuit employing differential signaling are reduced. The receiving circuit converts a first signal and a second signal which are supplied through differential signaling into a third signal which is a single-ended signal and outputs the third signal. The receiving circuit includes an operational amplifier, a first element, a first transistor, and a first circuit. The first element is connected to the first circuit through a first node to which the first transistor is connected. The first signal and the second signal that is the inverse of the first signal are supplied to the operational amplifier. The operational amplifier supplies an output signal to the first element, and a first preset potential is supplied to the first node through the first transistor. A signal including variations of the operational amplifier is stored in the first element in accordance with the first preset potential. The first circuit that is supplied with the first preset potential determines an initial value of the third signal without being influenced by the signal including variations of the operational amplifier.

An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.