Patent classifications
H03F3/42
STABILIZED NON-INDUCTIVE VOLTAGE BOOST CONVERTER OPERATING AT MOS SUB-THRESHOLD VOLTAGE FROM ANALAGOUS MICROPOWER PYROELECTRIC DEVICE
Disclosed herein is a non-Inductive voltage boost-converter (NVBC) for micro-power energy harvesting systems for energy storage and delivery applications. Current devices deliver a wide-range of micro-power having only up to 0.8V peak-voltage, but nominally 0.45V in lab test conditions. This voltage is not adequate in charging storage cells such as rechargeable batteries and also driving electronic circuits. Technology is in demand where a boost-converter must operate at MOS sub-threshold voltage (Sub-V.sub.TH) limits. Disclosed herein is a novel NVBC device that has eliminated the need of an inductor coil and associated high-speed switching circuits; thus achieving higher efficiency. The disclosed invention applies a simple self-synchronizing technique to adapt the NVBC automatically to the low-frequency energy signal of a pyroelectric device. A novel NVBC is presented for stabilized output of NVBC (S-NVBC). In an embodiment, the S-NVBC achieves an efficiency of 86%.
SEMICONDUCTOR DEVICES HAVING A PLURALITY OF UNIT CELL TRANSISTORS THAT HAVE SMOOTHED TURN-ON BEHAVIOR AND IMPROVED LINEARITY
A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
Semiconductor devices having a plurality of unit cell transistors that have smoothed turn-on behavior and improved linearity
A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.
POWER AMPLIFIER AND METHOD OF OPERATING THE POWER AMPLIFIER
A power amplifier includes an operational amplifier, a ramp generator communicatively coupled to both a first comparator and a second comparator; the first comparator further communicatively coupled to a negative output port of the operational amplifier; the second comparator further communicatively coupled to a positive output port of the operational amplifier; a first inverter communicatively coupled to the first comparator; a second inverter communicatively coupled to the second comparator; wherein the first inverter is communicatively coupled to both a positive input port of the operational amplifier via a first resistor and coupled to a negative input port of the operational amplifier via a fourth resistor; and the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor.
Power amplifier and method of operating the power amplifier
A power amplifier includes an operational amplifier, a ramp generator communicatively coupled to both a first comparator and a second comparator; the first comparator further communicatively coupled to a negative output port of the operational amplifier; the second comparator further communicatively coupled to a positive output port of the operational amplifier; a first inverter communicatively coupled to the first comparator; a second inverter communicatively coupled to the second comparator; wherein the first inverter is communicatively coupled to both a positive input port of the operational amplifier via a first resistor and coupled to a negative input port of the operational amplifier via a fourth resistor; and the second inverter is communicatively coupled to both the positive input port of the operational amplifier via a second resistor and connected to the negative input port of the operational amplifier via a third resistor.
Oscillator circuit using comparator
An oscillator circuit uses a comparator, and the oscillator circuit controls charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and enables the comparator output to follow a relatively high-frequency control signal that is input externally. The oscillator circuit uses a comparator having a differential unit and a gain unit. The oscillator circuit includes a charge-discharge control unit that connects to the output of the differential unit and is configured to control charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET (N2) serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and an output control unit configured to control the output of the gain unit.
Stacked power amplifiers using core devices
A power amplifier includes an input terminal configured to receive a low voltage input signal, an output terminal configured to output a high voltage output signal, and a plurality of amplifiers stacked in series between a first voltage terminal and a second voltage terminal. Each of the amplifiers includes an input capacitor, an output capacitor, an input coupled to the input terminal through the input capacitor, an output coupled to the output terminal through the output capacitor, and a feedback element coupled between the input and the output of the amplifier.
Amplifier arrangement and switched capacitor integrator
An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second differential stage and the second complementary differential stage are symmetrically connected to form respective first, second, third and fourth current paths. A pair of output terminals is coupled to the first and the fourth current path. Gate terminals of the transistors are coupled to a respective pair of input terminals.
MATRIX POWER AMPLIFIER
A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.
OSCILLATOR CIRCUIT USING COMPARATOR
An oscillator circuit uses a comparator, and the oscillator circuit controls charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and enables the comparator output to follow a relatively high-frequency control signal that is input externally. The oscillator circuit uses a comparator having a differential unit and a gain unit. The oscillator circuit includes a charge-discharge control unit that connects to the output of the differential unit and is configured to control charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET (N2) serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and an output control unit configured to control the output of the gain unit.