In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (R.sub.DEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (R.sub.PTAT) of the differential amplifier stage, a third resistor (R1.sub.PTAT) of the scaling amplifier stage, and a fourth resistor (R2.sub.PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.

Improved dither detection, measurement, and voltage bias adjustments for an electro-optical modulator are described. The electro-optical modulator generally includes RF electrodes and phase heaters interfaced with semi-conductor waveguides on the arms of Mach-Zehnder interferometers, where a processor is connected to output a bias tuning voltage to the electro-optical modulator for controlling optical modulation. A variable gain amplifier (VGA) can be configured with AC coupling connected to receive a signal from a transimpediance amplifier (TIA) that is configured to amply a photodetector signal from an optical tap that is used to measure an optical signal with a dither signal. The analog to digital converter (ADC) can be connected to receive output from the VGA. The processor can be connected to receive the signal from the ADC and to output the bias tuning voltage based on evaluation of the signal from the tap.

Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

Amplifier devices includes a first amplifier connected to receive an input voltage. The first amplifier outputs an internal voltage. These structures also include a second amplifier having an input node connected to receive the internal voltage and an output node outputting an output voltage. A resistive feedback loop is connected to the input node and the output node of the second amplifier. A first cross-coupled bandwidth boosting stage is connected to the input node of the second amplifier and a second cross-coupled bandwidth boosting stage connected to the output node of the second amplifier. The cross-coupled bandwidth boosting stages form a distributed differential positive feedback structure.

A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

An amplifier includes a first stage and a second stage. The first stage includes a first output, and a second output. The second stage includes a first transistor, a second transistor, and a common-mode circuit. The first transistor includes a drain coupled to the first output of the first stage. The second transistor includes a drain coupled to the second output of the first stage. The common-mode circuit includes a reversible current mirror circuit coupled to the drain of the first transistor and the drain of the second transistor.

The present disclosure provides a battery detection device. The detection circuit is disposed on the battery and produces an impedance value variation quantity according to a deformation of the battery. The detection circuit includes four connection nodes. The first connection node and the third connection node are connected with the battery. A voltage variation quantity is produced between the second connection node and the fourth connection node according to the impedance value variation quantity. The protection circuit is connected with the second connection node and the fourth connection node. The protection circuit is in an ON state when the voltage variation quantity is greater than or equal to a cut-off voltage. The protection circuit is in an OFF state when the voltage variation quantity is less than the cut-off voltage, so that an operation state of the battery is changed accordingly.

A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals. The latches receive two delayed input signals provided by the delay circuits based upon the feedback signals.

A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.

A high-frequency high-linear input buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a signal panning unit. A gate terminal of the first MOS transistor is used as an input terminal of the buffer. A current input terminal of the first MOS transistor is connected to a current output terminal of the second MOS transistor. A current output terminal of the first MOS transistor is connected to a current input terminal of the third MOS transistor. A current input terminal of the second MOS transistor is connected to a gate terminal of the third MOS transistor. An input terminal of the signal panning unit is connected to an input terminal of the buffer. An output terminal of the signal panning unit is connected to a gate terminal of the second MOS transistor. An output terminal of the third MOS transistor is connected to ground.