Systems and methods for operating a communication device. The methods comprise: obtaining a signal; allowing the signal to pass through a junction of a communication path to which a reflective frequency selective limiter is coupled; attenuating unwanted components of the signal using the reflective frequency selective limiter; and reflecting remaining components of the signal by the reflective frequency selective limiter so that the remaining components travel downstream along the communication path.

A tunable frequency selective limiter is disclosed. In one or more embodiments, the tunable frequency selective limiter includes a first electrically conductive path. The tunable frequency selective limiter also includes a ferrimagnetic layer disposed adjacent to the first electrically conductive path. The tunable frequency selective limiter further includes a second electrically conductive path coiled around the first electrically conductive path and the ferrimagnetic layer. An electromagnetic current transmitting through the second electrically conductive path produces a magnetic field coupled to the ferrimagnetic layer. The tunable frequency selective limiter further includes a dielectric layer, wherein the ferrimagnetic layer is disposed on the dielectric layer. The portions of the second electrically conductive path that are at the interface of the dielectric layer and the ferrimagnetic layer may be embedded into the dielectric layer or may be disposed on the surface of the dielectric layer.

A protection circuit configured to protect delicate electronics from high power signals is disclosed herein. To that end, the protection circuit includes a limiter circuit comprising a phase changing material to prevent high power signals from reaching one or more electronic circuits. The phase changing material assumes a limiting state automatically when an energy of an applied signal exceeds a threshold, which limits the energy of the signal passed on to any associated electronics.

An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.

An apparatus includes an input port, an output port, a first bias input, a first shunt PIN diode, a first radio frequency (RF) choke inductor, and a first direct current (DC) blocking capacitor. The input port may be connected to the output port, a first terminal of the first shunt PIN diode, and a first terminal of the first RF choke inductor. A second terminal of the first RF choke inductor is connected to a first terminal of the first DC blocking capacitor and the first bias input. A second terminal of the first shunt PIN diode and a second terminal of the first DC blocking capacitor are connected to a circuit ground potential. A first bias voltage having a magnitude lower than a knee voltage of the first shunt PIN diode is applied at the first bias input.

An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.

A frequency selective limiter (FSL) having an input port and an output port can comprise a plurality of vertically stacked transmission line structures. Each of the transmission line structures can be electrically coupled to a transmission line structure disposed directly above it and with a first one of the plurality of vertically stacked transmission line structures having one end corresponding to the FSL input port and a second one of the plurality of vertically stacked transmission line structures having one end corresponding to the FSL output port. Each of the plurality of vertically stacked transmission line structures can comprise a magnetic material having first and second opposing surfaces and one or more conductors disposed on at least one of the surfaces of the magnetic material.

A frequency selective limiter (FSL) is provided having a transmission line structure with a tapered width. The FSL includes a substrate having a magnetic material, a signal (or center) conductor disposed on the substrate and first and second ground plane conductors disposed on the substrate. The signal conductor having a first end with a first width and a second end with a second different width such that the signal conductor is provided having a taper between the first and second ends of the signal conductor. First and second ground plane conductors are spaced apart from first and second edges of signal conductor, respectively, by a distance that changes from the first end of signal conductor to the second end of signal conductor such that signal conductor, and first and second ground plane conductors form a co-planar waveguide transmission line.

A protection circuit configured to protect delicate electronics from high power signals is disclosed herein. To that end, the protection circuit includes a limiter circuit comprising a phase changing material to prevent high power signals from reaching one or more electronic circuits. The phase changing material assumes a limiting state automatically when an energy of an applied signal exceeds a threshold, which limits the energy of the signal passed on to any associated electronics.

A two-stage high-power RF limiter circuit for an RF signal receiver incorporates a heavy limiting stage to limit high energy pulses of a received RF signal to a desired power threshold over a sustained time period, while a light limiting stage reacts quickly to high energy pulses to reduce spike leakage associated with the slower reaction time of the heavy limiting stage. Both heavy and light limiting stages incorporate PIN diodes biased to a voltage just below the desired power threshold (the light limiter biased to a slightly higher voltage than the heavy limiter) so the PIN diodes do not activate until power levels are high enough to warrant limiting. The holdoff voltage across the PIN diodes is maintained by Zener diodes biased to a voltage corresponding to the power threshold, allowing the PIN diodes to self-bias once the power threshold is reached.