Example embodiments provide a process that includes one or more of receiving an audio signal at a feedback compressor circuit, multiplying the received audio signal with a power feedback signal to create a product audio signal, wherein the feedback signal comprises a low-pass filtered signal, applying a power amplifier to the product audio signal, and providing the amplified product audio signal as an output signal to a speaker.

A leveling equalizer includes a graphic equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a gain control circuit. The graphic equalizer circuit processes a first input signal and output a first output signal and a second output signal. The first multiplication circuit multiplies the first output signal and one of an adjustable gain value and a fixed gain value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and another of the adjustable gain value and the fixed gain value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The gain control circuit dynamically adjusts the adjustable gain value according to the equalizer output signal.

A network element of a cable television network includes at least a first and a second upstream amplifier stage, a first attenuator and a first equalizer between the first and the second amplifier stage, and a second attenuator after the second upstream amplifier stage in upstream signal path direction. A target value is determined for total attenuation of the components of the amplifier. The total attenuation is a sum of attenuations of the first attenuator, the first equalizer, and the second attenuator. The attenuation of the first equalizer is preset. The attenuation of the first attenuator is set to a maximum value such the sum of the attenuations of the first attenuator and the first equalizer is below a first threshold value. The attenuation of the second attenuator is set such that the total attenuation reaches the target value.

The present invention provides a common-mode rejection ratio and gain trimming circuit of differential amplifier, comprising: a first trimming unit and a second trimming unit coupled between an in-phase input voltage and a reference voltage, wherein the first trimming unit and the second trimming unit are coupled to a positive input terminal of the differential amplifier by means of tap switches; a third trimming unit and a fourth trimming unit coupled between tan inverting input voltage and an output terminal of the differential amplifier, wherein the third trimming unit and the fourth trimming unit are coupled to a negative input terminal of the differential amplifier by means of tap switches; wherein, the first trimming unit, the second trimming unit, the third trimming unit, and the fourth trimming unit comprise: a first trimming resistor string and a second trimming resistor string coupled in series; the first trimming resistor string is coupled in parallel with a first trimming auxiliary resistor string, and the second trimming resistor string is coupled in parallel with a second trimming auxiliary resistor string; wherein, the second trimming resistor string of the first trimming unit is coupled to the second trimming resistor string of the second trimming unit, and the second trimming resistor string of the third trimming unit is coupled to the second trimming resistor string of the fourth trimming unit.

In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.

An amplifier circuit having an adjustable gain is provided. The amplifier circuit includes an input terminal, an output terminal, an amplifier, and an attenuation circuit. The input terminal receives an input signal, which is in turn received by an input terminal of the amplifier. An output terminal of the amplifier outputs the input signal that is amplified. The attenuation circuit is coupled between the output terminal of the amplifier and the output terminal to provide a plurality of attenuation to the input signal that is amplified and generate a first attenuation signal, or between the input terminal and the output terminal to provide the plurality of attenuations to the input signal and generate a second attenuation signal. A difference between an impedance value of the input terminal of the attenuation circuit and an impedance value of the output terminal of the attenuation circuit is within a predetermined range.

Methods and devices to support multiple gain states in amplifiers are described. The methods and devices are based on implementing a feedback element in the amplifier and adjusting the impedance of the feedback element to provide a desired gain while maintaining the overall performance of the amplifier and reducing degradation of the S12 parameter. The feedback element includes an adjustable attenuator and a tunable resistive element. The adjustable attenuator is provided in a path that is common to the feedback path and the bypass path of the amplifier. Exemplary implementations of adjustable attenuators are also presented.

A network element of a cable television network includes at least a first and a second upstream amplifier stage, a first attenuator and a first equalizer between the first and the second amplifier stage, and a second attenuator after the second upstream amplifier stage in upstream signal path direction. A target value is determined for total attenuation of the components of the amplifier. The total attenuation is a sum of attenuations of the first attenuator, the first equalizer, and the second attenuator. The attenuation of the first equalizer is preset. The attenuation of the first attenuator is set to a maximum value such the sum of the attenuations of the first attenuator and the first equalizer is below a first threshold value. The attenuation of the second attenuator is set such that the total attenuation reaches the target value.

Temperature compensation circuits and methods for adjusting one or more circuit parameters of a power amplifier (PA) to maintain approximately constant Gain versus time during pulsed operation sufficient to substantially offset self-heating of the PA. Some embodiments compensate for PA Gain “droop” due to self-heating using a Sample and Hold (S&H) circuit. The S&H circuit samples and holds an initial temperature of the PA at commencement of a pulse. Thereafter, the S&H circuit generates a continuous measurement that corresponds to the temperature of the PA during the remainder of the pulse. A Gain Control signal is generated that is a function of the difference between the initial temperature and the operating temperature of the PA as the PA self-heats for the duration of the pulse. The Gain Control signal is applied to one or more adjustable or tunable circuits within a PA to offset the Gain droop of the PA.

A method for calibrating a fully-differential input system may include determining a first voltage of a first node of the fully-differential input system, wherein the first node is coupled at the first node to a plurality of first resistors in a first star configuration, determining a second voltage of a second node of the fully-differential input system, wherein the second node is coupled at the second node to a plurality of second resistors in a second star configuration, each resistor of the plurality of second resistors corresponding to a respective resistor of the plurality of first resistors, and trimming individual resistances of the plurality of first resistors and the plurality of second resistors in order to maintain a difference of a first voltage at the first node and a second voltage of the second node at approximately zero.