A differential current conveyor circuit includes two or more single-ended current conveyor stages and a common bias stage. First and second switches are set between the control terminals of the transistors in the common bias stage and a respective one of a first and a second coupling line of the single ended stages can be switched between the following: a reset state of the circuit with the transistors in the common bias stage coupled to the first and second coupling lines with the single-ended stages set to a bias condition; and a sensing state of the circuit with the transistors in the common bias stage decoupled from the first and second coupling lines, with the single-ended stages in a high impedance state with the control terminals of the input transistors of the single ended stages capacitively coupled to the input terminal.

A second-order all-pass network has at least three Second Generation Current Conveyors (CCIIs). A network input is connected or connectable to a Y port of a first CCII, a Z port of the first CCII is connected to a Y port of a second CCII, an X port of the first CCII is connected to a Y port of a third CCII, and a network output is connected or connectable, directly or indirectly, to a Z port of the second CCII. The X port of the first CCII is connected via a first network element to ground, the Z port of the first CCII is connected via a second network element to ground, an X port of the third CCII is connected via a third network element to ground, and an X port of the second CCII is connected via a fourth network element to ground.

A differential current conveyor circuit includes two or more single-ended current conveyor stages and a common bias stage. First and second switches are set between the control terminals of the transistors in the common bias stage and a respective one of a first and a second coupling line of the single ended stages can be switched between the following: a reset state of the circuit with the transistors in the common bias stage coupled to the first and second coupling lines with the single-ended stages set to a bias condition; and a sensing state of the circuit with the transistors in the common bias stage decoupled from the first and second coupling lines, with the single-ended stages in a high impedance state with the control terminals of the input transistors of the single ended stages capacitively coupled to the input terminal.