An apparatus is disclosed for bidirectional amplification with phase-shifting. In example implementations, an apparatus includes a phase shifter with a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between a first plus node and a second minus node, a second transistor coupled between a first minus node and a second plus node, a third transistor coupled between the first plus node and the second minus node, and a fourth transistor coupled between the first minus node and the second plus node. The bidirectional amplifier also includes a fifth transistor coupled between the first plus node and the second plus node, a sixth transistor coupled between the first minus node and the second minus node, a seventh transistor coupled between the first plus node and the second plus node, and an eighth transistor coupled between the first minus node and the second minus node.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

An apparatus is disclosed for phase-shifting signals. In example implementations, the apparatus includes a phase shifter. The phase shifter includes a first port, a second port, a vector modulator coupled to the first port, and a signal phase generator. The signal phase generator includes multiple amplifiers coupled between the vector modulator and the second port. The signal phase generator also includes multiple capacitors that couple the multiple amplifiers together to form a loop. Each respective capacitor of the multiple capacitors is coupled between a respective pair of consecutive amplifiers of the multiple amplifiers to form the loop.

An apparatus is disclosed for phase-shifting signals. In example implementations, the apparatus includes a phase shifter. The phase shifter includes a first port, a second port, a vector modulator coupled to the first port, and a signal phase generator. The signal phase generator includes multiple amplifiers coupled between the vector modulator and the second port. The signal phase generator also includes multiple capacitors that couple the multiple amplifiers together to form a loop. Each respective capacitor of the multiple capacitors is coupled between a respective pair of consecutive amplifiers of the multiple amplifiers to form the loop.

Apparatus and associated methods relate to a low-noise wideband active phase shifter. The low-noise wideband active phase shifter includes first and second transconductance cells, a fixed LC series network and a tunable LC series network configured to form an all-pass lattice network. The first and second transconductance cells, each include a transistor, a feedback network, and a transistor biasing network. The transistor has an input terminal and an output terminal. The negative feedback network electrically couples the input and output terminals of the transistor. The biasing network provides input and output biasing of the transistor. The fixed LC series network connects between the first and the second transconductance cells. The tunable LC series network connects between the first and the second transconductance cells.

Apparatus and associated methods relate to a low-noise wideband active phase shifter. The low-noise wideband active phase shifter includes first and second transconductance cells, a fixed LC series network and a tunable LC series network configured to form an all-pass lattice network. The first and second transconductance cells, each include a transistor, a feedback network, and a transistor biasing network. The transistor has an input terminal and an output terminal. The negative feedback network electrically couples the input and output terminals of the transistor. The biasing network provides input and output biasing of the transistor. The fixed LC series network connects between the first and the second transconductance cells. The tunable LC series network connects between the first and the second transconductance cells.

Apparatus and methods for vector modulator phase shifters are provided. In certain embodiments, a phase shifter includes a quadrature filter that filters a differential input signal to generate a differential in-phase (I) voltage and a differential quadrature-phase (Q) voltage, an in-phase variable gain amplifier (I-VGA) that amplifies the differential I voltage to generate a differential I current, a quadrature-phase variable gain amplifier (Q-VGA) that amplifies the differential Q voltage to generate a differential Q current, and a current mode combiner that combines the differential I voltage and the differential Q voltage to generate a differential output signal. A phase difference between the differential output signal and the differential input signal is controlled by gain settings of the I-VGA and the Q-VGA.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.