Systems and methods for a tunable impedance are provided. A tunable impedance includes a transistor assembly having two terminals and a control input. The transistor assembly includes one or more transistors electrically connected between the two terminals to provide a first impedance between the two terminals, based upon a control signal. One or more replica transistors react to the control signal in a similar fashion as the transistor assembly, to provide a replica impedance based upon the control signal. A control circuit is configured to generate the control signal based upon a voltage across the replica transistor(s) and/or a current through the replica transistor(s).

A circuit for realizing a precision and linear floating resistor, using MOSFET devices, is disclosed. A linear floating voltage-controlled resistor (LFVCR) is realized using a MOSFET with a gate drive means and a substrate drive means to provide a feedback of the common-mode voltage across the source-drain terminals to the gate and substrate terminals. Two such LFVCR circuits using matched MOSFET devices having independent substrates, along with an op-amp based negative feedback loop, are used to realize a continuously variable precision and linear floating resistor, whose value can be controlled by a combination of variable voltage, current, and resistor. Further embodiments are disclosed for realizing a resistor mirror circuit with multiple floating resistors, improving the linearity by using LFVCR circuits with complementary MOSFET devices, realizing a resistor with scaled-up resistance and extended voltage range, and realizing a resistor with scaled-down resistance and extended current range.

A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be field-programmable, i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.

An in-phase/quadrature (I/Q) clock generator is described. The I/Q clock generated includes a poly-phase filter configured to generate a four-phase quadrature clock signal in response to a two-phase quadrature clock signal generated in response to a single-ended input clock signal. The I/Q clock generated also includes a phase interpolator configured to generate an output four-phase quadrature clock signal from the four-phase quadrature clock signal. The I/Q clock generated further includes a poly-phase filter tune circuit coupled to an output of the phase interpolator. The poly-phase filter tune circuit is configured to generate a control voltage for the poly-phase filter to tune the four-phase quadrature clock signal from the poly-phase filter.

An electronic device includes a reference resistor, two first terminals between which the reference resistor is connected, and two second terminals between which a modified impedance value of the reference resistor is intended to be obtained. The electronic device also includes a first circuit that applies between the two second terminals a voltage substantially equal to that between the two first terminals, and a second circuit that flows between the two second terminals a second current the value of which corresponds to a fraction of a first current for flowing in the reference resistor between the two first terminals.

A circuit for realizing a precision and linear floating resistor, using MOSFET devices, is disclosed. A linear floating voltage-controlled resistor (LFVCR) is realized using a MOSFET with a gate drive means and a substrate drive means to provide a feedback of the common-mode voltage across the source-drain terminals to the gate and substrate terminals. Two such LFVCR circuits using matched MOSFET devices having independent substrates, along with an op-amp based negative feedback loop, are used to realize a continuously variable precision and linear floating resistor, whose value can be controlled by a combination of variable voltage, current, and resistor. Further embodiments are disclosed for realizing a resistor mirror circuit with multiple floating resistors, improving the linearity by using LFVCR circuits with complementary MOSFET devices, realizing a resistor with scaled-up resistance and extended voltage range, and realizing a resistor with scaled-down resistance and extended current range.

A non-linear impedance terminates a transmission line. The non-linear impedance may be implemented with a back-to-back connected inverter pair. The pair acts as a non-linear resistor. A process, voltage, temperature (PVT) tracking circuit may also be provided to improve PVT tracking, with resistance of transistors locked to a calibrated resistor. The replica circuit does not appear in the signal path, and does not add capacitive load.

A server farm has servers with at least one hybrid computing module operating at a system clock speed that optimally matches the intrinsic clock speed of a semiconductor die embedded within a high speed semiconductor chip stack or mounted upon the semiconductor carrier.

A pseudo resistor with tunable resistance including a first transistor and a second transistor is provided. The first transistor has a first terminal, a second terminal and a control terminal. The first terminal of the first transistor serves as a first terminal of the pseudo resistor. The control terminal of the first transistor receives a control voltage. The first transistor is controlled by the control voltage, such that the first transistor operates in a weak inversion region. The second transistor has a first terminal, a second terminal and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor and the control terminal of the second transistor are coupled to each other to serve as a second terminal of the pseudo resistor with tunable resistance. The second transistor operates in the weak inversion region.

A low-pass filter circuit is provided. The low-pass filter circuit includes a low-pass filter and a discharging circuit. The low-pass filter receives an input voltage signal through an input terminal of the low-pass filter circuit during a first period, performs a low-pass filter operation on the input voltage signal to generate a filtered voltage signal, and provides the filtered voltage signal to an output terminal of the low-pass filter circuit. The discharging circuit suppresses a leakage current flowing between the output terminal and a reference low voltage in response to the input voltage signal during the first period.