A digital interpolation filter delivering a series of output samples approximating a signal x(t) at sampling instants of the form (n+d)T s based on a series of input samples of the signal x(t) taken at sampling instants of the form nT s. Such a filter implements a transfer function in the Z-transform domain, H c<i/>d (Z−1), expressed as a linear combination between: a first transfer function H 1 d<i/>(Z−1) representing a Lagrange polynomial interpolation of the input samples implemented according to a Newton structure (100); and a second transfer function H 2 d (Z−1) representing another polynomial interpolation of the input samples implemented according to another structure comprising at least the Newton structure; the linear combination being a function of at least one real combination parameter c.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

This disclosure relates to evaluating and improving performance of a control implementation on a quantum processor comprising multiple qubits in the presence of noise. A noise model decomposes noise interactions described by a multi-qubit noise Hamiltonian into multiple contributory noise channels. Each channel generates noise dynamics described by a unique noise-axis operator. For a given control implementation, a unique filter function represents susceptibility of the multi-qubit system to the associated noise dynamics. The filter functions are based on a frequency transformation of the noise axis operator of the corresponding noise channel to thereby evaluate the performance of the control implementation. An optimised control sequence is based on the filter function to reduce the susceptibility of the multi-qubit system to the noise channels, thereby reducing the effective interaction with the multi-qubit noise Hamiltonian. The optimised control sequence controls the quantum processor to thereby improve the performance of the control implementation.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

Systems and methods for direct signal down-conversion and decimation in a digital receiver. The digital receiver produces a decimated passband version of the signal without the problems associated with use of digital mixers. The digital receiver includes a passband-to-passband decimator/down-converter that implements an algorithm which takes the signal band (frequency and bandwidth or lower and upper frequencies) where a signal is present and produces a decimation rate and phase for use by a low-pass mixer-free down-conversion. The digital receiver technology may be efficiently implemented on a digital signal processor or field-programmable gate array.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting.

Systems and methods for direct signal down-conversion and decimation in a digital receiver. The digital receiver produces a decimated passband version of the signal without the problems associated with use of digital mixers. The digital receiver includes a passband-to-passband decimator/down-converter that implements an algorithm which takes the signal band (frequency and bandwidth or lower and upper frequencies) where a signal is present and produces a decimation rate and phase for use by a low-pass mixer-free down-conversion. The digital receiver technology may be efficiently implemented on a digital signal processor or field-programmable gate array.