The present invention provides a signal processing circuit including a control unit, a transmission drive unit, an analog switch array, a signal amplification unit, a detection integration unit that are connected in sequence, and a transceiver antenna connected to the analog switch array. The control unit includes an analog-to-digital converter. The signal processing circuit further includes a level conversion unit arranged between the analog-to-digital converter and the signal amplification unit, the level conversion unit is configured to linearly convert signals received by the transceiver antenna, and transmit the linearly converted signals to the analog-to-digital converter. The signal processing circuit has advantages of low cost, fast handwriting speed, and less cursor wobble. The present invention also provides a position detecting device using the same.

A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.

Trans-filter/Detectors are extremely sensitive circuits that recover exponentially modulated signals buried in noise. They can be used wherever Matched Filter/Coherent Detectors are used and operate at negative input signal-to-noise ratios to recover RADAR, SONAR, communications, or data signals, as well as reduce phase noise of precision oscillators. Input signal and noise is split into two paths where complementary derivatives are extracted. Outputs of the two paths are equal in amplitude and 180 degrees relative to each other at the band center frequency. The outputs are summed, causing stationary in-band noise to be reduced by cancellation while exponentially modulated signals are undiminished. Trans-filters are Linear Time Invariant circuits, have no noise x noise threshold and can be cascaded, increasing output signal-to-noise ratio prior to detection. Trans-filters are most sensitive to all types of digital modulation, producing easily detected polarized pulses synchronous with data transitions. Trans-filters do not require coherent conversion oscillators and complex synchronizing circuits.

Trans-filter/Detectors are extremely sensitive circuits that recover exponentially modulated signals buried in noise. They can be used wherever Matched Filter/Coherent Detectors are used and operate at negative input signal-to-noise ratios to recover RADAR, SONAR, communications, or data signals, as well as reduce phase noise of precision oscillators. Input signal and noise is split into two paths where complementary derivatives are extracted. Outputs of the two paths are equal in amplitude and 180 degrees relative to each other at the band center frequency. The outputs are summed, causing stationary in-band noise to be reduced by cancellation while exponentially modulated signals are undiminished. Trans-filters are Linear Time Invariant circuits, have no noise x noise threshold and can be cascaded, increasing output signal-to-noise ratio prior to detection. Trans-filters are most sensitive to all types of digital modulation, producing easily detected polarized pulses synchronous with data transitions. Trans-filters do not require coherent conversion oscillators and complex synchronizing circuits.

A signal processing system is described. The signal processing system includes at least one signal processing path and a control module. The at least one signal processing path includes at least one signal input and at least two filter units. The at least two filter units include at least one hardware filter unit. The at least one signal input is connectable to at least one external electronic component. The control module is connected to the signal input and to the at least two hardware filter units. The control module is configured to determine a frequency response deviation being associated with the at least one external electronic component. The control module further is configured to reconfigure the at least one hardware filter unit such that the frequency response deviation is compensated at least partially. Further, a signal processing method for adapting filter coefficients of a signal processing system is described.

Droop caused by a filter may be compensated by applying a pre-filter to the audio signal that cancels out, at least in part, the droop caused by the filter. The pre-filter may implement magnitude compensation that causes an approximately flat passband response when the pre-filtered signal is passed through the filter. The pre-filter may be applied to one-bit wide data streams, such as high-fidelity direct stream digital (DSD) audio data or other one-bit wide data such as pulse-density modulation (PDM) encoded data. The pre-filtering and filtering may be implemented in components of an audio processor, such as in a digital-to-analog converter (DAC). The pre-filtering may include upsampling the one-bit wide data to form symbols and substituting an eighth bit of the symbol with an inverted version of an earlier-received bit.

A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by the multiplying factor adjustment value.

This disclosure relates to evaluating and improving performance of a control implementation on a quantum processor comprising multiple qubits in the presence of noise. A noise model decomposes noise interactions described by a multi-qubit noise Hamiltonian into multiple contributory noise channels. Each channel generates noise dynamics described by a unique noise-axis operator. For a given control implementation, a unique filter function represents susceptibility of the multi-qubit system to the associated noise dynamics. The filter functions are based on a frequency transformation of the noise axis operator of the corresponding noise channel to thereby evaluate the performance of the control implementation. An optimised control sequence is based on the filter function to reduce the susceptibility of the multi-qubit system to the noise channels, thereby reducing the effective interaction with the multi-qubit noise Hamiltonian. The optimised control sequence controls the quantum processor to thereby improve the performance of the control implementation.

A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.

A mechanism is included for jointly determining filter coefficients for Finite Impulse Response (FIR) filters in a Linear, Memory-less Non-linear (LNL), Linear compensator. Calibration signals are applied to a signal converter input in a test and measurement system. Non-linear signal components are determined in signal output from the signal converter. Non-linear filter components are determined at the LNL compensator based on the calibration signals. The non-linear signal components are then compared to the non-linear filter components. The comparison is then resolved to determine filter coefficients for first stage Finite Impulse Response (FIR) filters and second stage FIR filters in the LNL.