A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.

A digital filter circuit is described. The digital filter circuit includes a pre-adder circuit, a convolution circuit, and a post-adder circuit. The pre-adder circuit includes a number of n pre-adder sub-circuits, wherein n is an integer greater than or equal to 2. The convolution circuit includes a number of m convolution sub-circuits, wherein m is an integer. The post-adder circuit includes a number of k post-adder sub-circuits, wherein k is an integer greater than or equal to 2. The number m of convolution sub-circuits is greater than the number n of pre-adder sub-circuits of the pre-adder circuit. The number m of convolution sub-circuits is greater than the number k of post-adder sub-circuits of the post-adder circuit. Further, an electronic device is described.

A digital filter circuit is described. The digital filter circuit includes a digital filter input, at least two finite impulse response (FIR) filter circuits, and a connection circuit. The digital filter input is configured to receive a digital input signal set having a data parallelism. The at least two FIR filter circuits are configured to process the digital input signal set at least partially. The at least two FIR filter circuits include a pre-adder sub-circuit, a convolution sub-circuit, and a post-adder sub-circuit, respectively. The connection circuit is configured to selectively connect the at least two FIR filter circuits based on the data parallelism of the digital input signal set.

A system and method for symmetrical filtering of an input string may include loading, into at least one vector register, in a single read cycle, a subset of right-side data elements and a subset of left-side data elements of the input string. The input string may be stored sequentially in a memory unit. The right-side data elements and the left-side data elements may be equally distant from the center of the input string and may be separated by a whole number of rows in the memory. The system and method may include performing filtering of the input string using a symmetrical filter with the loaded right-side data elements and left-side data elements.

A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.

A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.

There is provided a data processing apparatus and method. The data processing apparatus comprises a filter circuit comprising storage circuitry to store program counter values and to assert a trigger signal in response to a lookup operation using a current program counter value hitting in the storage circuitry. The processing apparatus comprises a processing unit to generate an output in response to the trigger signal. The processing apparatus is provided with resolution circuitry, associated with a downstream processing stage, to determine whether the output is of use, and in that event to assert a false miss indication in the absence of the processing unit having been triggered to produce the output. The filter circuit is configured to maintain a trigger sensitivity metric in dependence on the false miss indication, and the chosen number of bits employed when performing the lookup operation is dependent on the trigger sensitivity metric.

Prism signal processing is a new FIR filtering technique that can offer a fully recursive calculation and elegant filter design. Its low design and computational cost may be particularly suited to the autonomous signal processing requirements for the Internet of Things. Arbitrarily narrow band-pass filters may be designed and implemented using a chain of Prisms and a simple yet powerful procedure. Using the described method and system, an ultra-narrowband filter can be evaluated in fractions of a microsecond per sample on a desktop computer. To achieve this update rate using a conventional non-recursive FIR calculation would require supercomputer resources. FPGA embodiments of the system demonstrate computation efficiency and broad applications of the technique.

A filter circuit includes a processor configured to compare a current input value with a last-time output value, add a first correction value to the current input value and to the last-time output value if a comparison result between the current input value and the last-time output value is greater than a predetermined value, and add a second correction value smaller than the first correction value to the current input value and to the last-time output value if the comparison result is smaller than or equal to the predetermined value, and calculate a current output value based on the current input value and the last-time output value to each of which the first correction value or the second correction value has been added.

A filter circuit includes multiple registers, a switch circuit, multiple multipliers and a summation circuit. Each register is configured to store an input. The switch circuit is coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value. The count value is accumulated in response to reception of a new input of the filter circuit. The multipliers are coupled to the switch circuit. The inputs of the series of rearranged inputs are sequentially provided to the multipliers. Each multiplier is configured to generate a multiplication result according to the received input and a coefficient. The summation circuit is coupled to the multipliers and configured to sum up the multiplication results to generate an output.