A signal conversion from an input signal to an output signal where the filter used is factorized so that the conversion comprises determining 1) only a first factor at each sampling time of the input signal, where this first factor is independent on the sampling times of the output signal, and 2) only a second factor at each sampling time of the output signal, where this second factor is independent of the sampling times of the input signal. This reduces the computational load for this conversion. In addition, for most filters, the factors may be calculated recursively further increasing the computational load and also reducing the storage requirements. This allows for instantaneous changes in the sampling rates or non-uniform sampling rates with low computational requirements and low memory usage.

Provided is a digital filter circuit in which a filter coefficient can be easily changed, for which circuit scale and power consumption can be reduced, and which carries out digital filter processing in a frequency domain. This digital filter circuit includes: a separating circuit for separating a first complex number signal, of a frequency domain that was subjected to Fourier transform, into a real number portion and an imaginary number portion; a filter coefficient generating circuit for generating a first frequency domain filter coefficient from a first input filter coefficient and a third input filter coefficient, and for generating a second frequency domain filter coefficient from a second input filter coefficient and the third input filter coefficient; a first filter that filters the separated real number portion using the first frequency domain filter coefficient; a second filter that filters the separated imaginary number portion using the second frequency domain filter coefficient; and a combining circuit for combining the output from the two filters.

An interleaved cascaded integrator-comb (“CIC”) filter receives an interleaved sensor output signal, including a plurality of digitized sensor signals at an input clock rate. An integrator of the interleaved CIC filter processes the interleaved signal to output an integrated interleaved signal. A downsampler of the interleaved CIC filter buffers portions of the integrated interleaved corresponding to a decimation rate for the interleaved signal. The portions of the signals are provided to a comb filter, which outputs a decimated interleaved signal.

A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.

A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L−1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.

A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

The present invention relates to a method and an apparatus for processing a signal, which are used for effectively reproducing a multimedia signal, and more particularly, to a method and an apparatus for processing a signal, which are used for implementing filtering for multimedia signal having a plurality of subbands with a low calculation amount. To this end, provided are a method for processing a multimedia signal including: receiving a multimedia signal having a plurality of subbands; receiving at least one proto-type filter coefficients for filtering each subband signal of the multimedia signal; converting the proto-type filter coefficients into a plurality of subband filter coefficients; truncating each subband filter coefficients based on filter order information obtained by at least partially using characteristic information extracted from the corresponding subband filter coefficients, the length of at least one truncated subband filter coefficients being different from the length of truncated subband filter coefficients of another subband; and filtering the multimedia signal by using the truncated subband filter coefficients corresponding to each subband signal and an apparatus for processing a multimedia signal using the same.

Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption.

A digital control circuitry for a MEMS gyroscope is provided. The digital control circuitry comprises a digital primary loop circuitry configured to process a digitized primary signal, a digital secondary loop circuitry configured to process a digitized secondary signal and a digital phase shifting filter circuitry configured to generate two phase shifted demodulation signals from the digitized primary signal. The digital secondary loop is configured to demodulate the digitized secondary signal using the two phase shifted demodulation signals.

An apparatus and method are disclosed for processing an audio signal. The apparatus includes an input interface, a digital filterbank having an analysis part and a synthesis part, a first phase shifter, a spectral envelope adjuster, a second phase shifter, and an output interface. The first phase shifter and the second phase shifter reduce a complexity of the digital filterbank, which includes both analysis and synthesis filters that are complex-exponential modulated versions of a prototype filter.