A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

A noise suppression circuit includes a resistor-capacitor (RC) filter where a resistive element of the RC filter has a first terminal configured to receive an input data stream and a second terminal coupled to a circuit node Vrc and a capacitive element coupled to the circuit node, a logic gate having an input coupled to the circuit node and an output configured to provide a filtered data stream, and a switch. The switch is configured to short out the resistive element of the RC filter when the input data stream and the filtered data stream are at a same value and not short out the resistive element when the input data stream and the filtered data stream are at different values.

Prism signal processing is a new FIR filtering technique that can offer a fully recursive calculation and elegant filter design. Its low design and computational cost may be particularly suited to the autonomous signal processing requirements for the Internet of Things. Arbitrarily narrow band-pass filters may be designed and implemented using a chain of Prisms and a simple yet powerful procedure. Using the described method and system, an ultra-narrowband filter can be evaluated in fractions of a microsecond per sample on a desktop computer. To achieve this update rate using a conventional non-recursive FIR calculation would require supercomputer resources. FPGA embodiments of the system demonstrate computation efficiency and broad applications of the technique.

A noise suppression circuit includes a resistor-capacitor (RC) filter where a resistive element of the RC filter has a first terminal configured to receive an input data stream and a second terminal coupled to a circuit node Vrc and a capacitive element coupled to the circuit node, a logic gate having an input coupled to the circuit node and an output configured to provide a filtered data stream, and a switch. The switch is configured to short out the resistive element of the RC filter when the input data stream and the filtered data stream are at a same value and not short out the resistive element when the input data stream and the filtered data stream are at different values.

Prism signal processing is a new FIR filtering technique that can offer a fully recursive calculation and elegant filter design. Its low design and computational cost may be particularly suited to the autonomous signal processing requirements for the Internet of Things. Arbitrarily narrow band-pass filters may be designed and implemented using a chain of Prisms and a simple yet powerful procedure. Using the described method and system, an ultra-narrowband filter can be evaluated in fractions of a microsecond per sample on a desktop computer. To achieve this update rate using a conventional non-recursive FIR calculation would require supercomputer resources. FPGA embodiments of the system demonstrate computation efficiency and broad applications of the technique.

Trans-filter/Detectors are extremely sensitive circuits that recover exponentially modulated signals buried in noise. They can be used wherever Matched Filter/Coherent Detectors are used and operate at negative input signal-to-noise ratios to recover RADAR, SONAR, communications or data signals. Input signal and noise is split into two paths where complementary derivatives are extracted. Outputs of the two paths are equal in amplitude and 180 degrees relative to each other at the band center frequency. The outputs are summed, causing stationary in-band noise to be reduced by cancellation while exponentially modulated signals are increased by addition. Trans-filters are Linear Time Invariant circuits, have no noise×noise threshold and can be cascaded, increasing in-band signal-to-noise ratio prior to detection. Trans-filters are most sensitive to all types of digital modulation, producing easily detected polarized pulses synchronous with data transitions. Trans-filters do not require coherent conversion oscillators and complex synchronizing circuits.

A 1st frequency reduction circuit of a filter of the invention downsamples the sampling rate of a signal source to a predetermined value to obtain a 1st PCM stream, a 1st frequency raising circuit raises the sampling rate of the 1st PCM stream to be the same as that of the signal source, a 1st delay circuit delays a stream of the signal source, such that its phase is the same as that of the 1st PCM stream, a 1st adder subtracts the frequency raised 1st PCM steam from the delayed stream of the signal source to obtain a passband 1, a j-th frequency reduction circuit downsamples the sampling rate of a (j1)-th PCM stream to a predetermined value to obtain a j-th PCM stream, wherein 2jn, a j-th frequency raising circuit raises the sampling rate of the j-th PCM stream to be the same as that of the (j1)-th PCM stream, a j-th delay circuit delays the (j1)-th PCM stream, such that its phase is the same as that of the j-th PCM stream, a j-th adder subtracts the frequency raised j-th PCM stream from the delayed (j1)-th PCM stream to obtain a passband j, and when j=n, the j-th PCM stream is a passband n+1.

Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.

Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.

A 1st frequency reduction circuit of a filter of the invention downsamples the sampling rate of a signal source to a predetermined value to obtain a 1st PCM stream, a 1st frequency raising circuit raises the sampling rate of the 1st PCM stream to be the same as that of the signal source, a 1st delay circuit delays a stream of the signal source, such that its phase is the same as that of the 1st PCM stream, a 1st adder subtracts the frequency raised 1st PCM steam from the delayed stream of the signal source to obtain a passband 1, a j-th frequency reduction circuit downsamples the sampling rate of a (j1)-th PCM stream to a predetermined value to obtain a j-th PCM stream, wherein 2jn, a j-th frequency raising circuit raises the sampling rate of the j-th PCM stream to be the same as that of the (j1)-th PCM stream, a j-th delay circuit delays the (j1)-th PCM stream, such that its phase is the same as that of the j-th PCM stream, a j-th adder subtracts the frequency raised j-th PCM stream from the delayed (j1)-th PCM stream to obtain a passband j, and when j=n, the j-th PCM stream is a passband n+1.