An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

To suppress an unstable operation of a device caused by filtering, an output selection unit is configured to acquire an unfiltered value representing an input signal (signal before filtering) stored in an input holding unit, a filtered value representing a signal acquired by filtering the input signal by a filtering unit, and a previous output value representing an output signal output at a previous time, select a middle value out of the filtered value, the unfiltered value, and the previous output value, and set the selected middle value as a current output value of an output signal.

The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate f.sub.s is lowered by dividing the ADC's output x(n) into M parallel data streams x.sub.i(n) of low data rate, and the ML samples in one clock circle is obtained by delaying the M parallel data streams x.sub.i(n) simultaneously by 1, 2, . . . , L periods of the synchronous clock, at last, the samples y.sub.i(n) of FIR filtering output is calculated according to the samples selected from the ML samples, and the filtered data y(n) of data rate f.sub.s is obtained by putting the samples y.sub.i(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.

The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

A signal processing circuit has a first signal loop with a first signal processing block and a first feedback path that extends around the first signal processing block, the first signal processing block having a frequency dependence that causes the first signal loop to generate a passband. A second signal processing block is downstream of the first signal loop. A second feedback path extends from downstream of the second signal processing block to upstream of the first signal processing block. In operation, the first feedback path reinforces a signal in the passband and the second feedback path conditions the signal at an output downstream of the first signal processing block.

To suppress an unstable operation of a device caused by filtering, an output selection unit is configured to acquire an unfiltered value representing an input signal (signal before filtering) stored in an input holding unit, a filtered value representing a signal acquired by filtering the input signal by a filtering unit, and a previous output value representing an output signal output at a previous time, select a middle value out of the filtered value, the unfiltered value, and the previous output value, and set the selected middle value as a current output value of an output signal.