An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

A storage apparatus of an associative array type that stores a large-sized value at a low cost is provided. The storage apparatus of the associative array type includes a first memory, a second memory that stores a value, and a third memory. The first memory stores a key and an address of the second memory. The address of the second memory is an address where the value corresponding to the key is stored. The third memory stores an address of the first memory. The address of the first memory is an address where the key corresponding to the value stored in the second memory is stored. The first memory further stores a flag that indicates whether or not the key has been registered.

The present disclosure relates to a concept of nonlinear signal processing which may be used for predistortion for RF power amplifiers. The concept includes generating time variant filter coefficients for a linear filter circuit based on a nonlinear mapping of an input signal, and filtering the input signal with the linear filter circuit using the time variant filter coefficients in order to generate a filtered output signal. Thus, it is proposed to implement a non-linear filter by a time-varying linear filter where the time-varying coefficients are derived from the input signal.

An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

An integrated circuit for generating an equalized signal, according to a channel, from serial data includes a shift register that extracts a symbol sequence from the serial data. A data storage stores values of an equalized digital signal corresponding to potential symbol sequences corresponding to a filter coefficient sequence. A lookup table outputs the equalized digital signal of a value corresponding to the extracted symbol sequence. A digital-to-analog converter (DAC) converts the equalized digital signal into the equalized signal. A controller refreshes the lookup table, based on at least one of values stored in the data storage and values included in the lookup table, in response to a control signal.

The present disclosure relates to a concept of nonlinear signal processing which may be used for predistortion for RF power amplifiers. The concept includes generating time variant filter coefficients for a linear filter circuit based on a nonlinear mapping of an input signal, and filtering the input signal with the linear filter circuit using the time variant filter coefficients in order to generate a filtered output signal. Thus, it is proposed to implement a non-linear filter by a time-varying linear filter where the time-varying coefficients are derived from the input signal.

An example circuit includes: a filter configured to process a digital signal through at least one stage; and a coefficient generator circuit configured to generate coefficients for the at least one stage of the filter. The coefficient generator circuit includes: a lookup-table (LUT) configured to output a differential sequence; an up-sampling holder circuit configured to up-sample and hold the differential sequence to generate an up-sampled differential sequence; and an accumulator configured to integrate the up-sampled differential sequence to generate the coefficients.

An example circuit includes: a filter configured to process a digital signal through at least one stage; and a coefficient generator circuit configured to generate coefficients for the at least one stage of the filter. The coefficient generator circuit includes: a lookup-table (LUT) configured to output a differential sequence; an up-sampling holder circuit configured to up-sample and hold the differential sequence to generate an up-sampled differential sequence; and an accumulator configured to integrate the up-sampled differential sequence to generate the coefficients.