The behavior of a NOS DAC and an analog filter may be emulated by electronic components of an integrated circuit (IC) by upsampling data and applying a digital filter to the upsampled data. For example, the IC may include a zero-order-hold circuit that upsamples data from a first input sample rate to a second, higher input rate. The upsampled data may be passed to an Asynchronous Sample Rate Converter (ASRC) that performs further upsampling (e.g., from 8*Fs-64*Fs). The upsampled data may be passed to a digital low pass filter. The digital low pass filter may emulate, for example, a response of a fifth order Butterworth analog filter to mimic the effect of analog processing. The IC may integrate the upsampling circuit, the low pass digital filter, a digital-to-analog converter (DAC) and an amplifier to provide an audio solution for playing high-fidelity music in a mobile device.

A method of increasing the sample rate of a digital signal by creating intermediate sample points between adjacent neighbouring sample points comprising the step of populating each of the intermediate sample points depending on a weighted influence of a predetermined number of the neighbouring sample points, the weighted influence being calculated by representing the digital signal or filter at the predetermined number of sample points at least in part by its cosine components, which are each represented by absolute values of a cosine function in the time domain substantially limited to half a waveform cycle at its mid-point; combining the aforementioned cosine components at each of the neighbouring sample points to obtain waveforms at each of the neighboring sample points; determining values for each of the waveforms at the intermediate sample points and combining the determined values at the intermediate sample point to derive the weighted influence.

A method of processing a digital signal includes providing a digital filter including neighbouring sample points and performing a sample rate increase on the digital filter to provide intermediate sample points between adjacent neighbouring sample points, said intermediate points being populated dependent on a weighted influence determined in the time domain of a predetermined number of the neighbouring sample points. The digital filter is applied to the signal where: i) one of the neighbouring sample points of the filter is applied to a corresponding sample point of the signal; ii) offset and neighbouring sample points of the signal are defined either side of the corresponding sample point, said offset points being offset in the time domain relative to the respective neighbouring sample points of the filter; and iii) the neighbouring sample points of the filter are applied to respective of the offset and neighbouring sample points of the signal.

A digital filter for filtering an input signal to form an output signal containing a coefficient multiplier and a moving-average filter. The coefficient multiplier is embodied to multiply values of the input signal by coefficients of the filter to form an intermediate signal. The moving-average filter is embodied to generate the output signal as a moving average of the intermediate signal.

Proposed is a transport vehicle including a traveling unit being moved along a first direction, a slide unit being driven for sliding in a second direction vertical to the first direction, a hand unit ascending and descending by a hoist combined with the slide unit and gripping the goods, and a control unit controlling driving of the traveling unit for traveling or driving of the slide unit for sliding, wherein the control unit applies a filter signal to an initial slide control signal for driving for sliding and controls driving of the hand unit for sliding through a drive control signal for sliding to which the filter signal is applied, and the filter signal includes a plurality of impulse signals and an interval between the impulse signals is determined as a value corresponding to a length of the hoist in linear interpolation on pre-stored period values on a per-hoist-length basis.

A method generates a delayed signal based on an input signal, and applies vector magnitude scaling to the delayed signal, generating one or more vector magnitude scaled signals. The input signal is added to the one or more vector magnitude scaled signals, generating one or more phase-shifted signals. Compensation scaling is applied to the one or more phase-shifted signals, generating one or more compensated signals. The input signal and the one or more compensated signals are combined, generating an interpolated output signal. The method may be implemented by a device or a system.

An interpolation filtering system implemented by a digital circuit is provided, it includes an interpolation filtering operation controller, a cascaded drive module, an intermediate result cache Random Access Memory (RAM), and a filter coefficient storage Read Only Memory (ROM). The intermediate result cache RAM is configured to store externally input data of the interpolation filtering system and intermediate results output by the filter operation modules. The filter coefficient storage ROM is configured to store filter coefficients required for calculation by the filter operation modules. The interpolation filtering operation controller is configured to control, under the drive of counting beats output by the cascaded drive module, the master state machine to select data of the intermediate result cache TAM or externally directly input data to be sent to the cascaded filter operation modules for accumulation operation, and to select the filter coefficients of the filter coefficient storage ROM for multiplication operation.

Embodiments of the present invention provide a digital signal processing apparatus, including an interpolator, an interpolating convolver, or the like, for providing a plurality of output samples or output values in parallel, such as P output samples provided by P Farrow cores, based on a set of input samples or input values, such as 2P+M−2 samples. The digital signal processing apparatus includes a sample distribution logic or structure configured to provide a plurality of subsets of the set of input samples to a plurality of processing cores, such as interpolation cores (e.g., Farrow cores) that perform processing operations associated with different time shifts, for example with respect to a reference time (e.g., a time associated with the input samples). The sample distribution logic includes a hierarchical tree structure having a plurality of hierarchical levels of splitting nodes.

As part of a signal processing event, the maximum frequency of an input signal can be determined with a processor. The maximum frequency can be compared to a value generated with a decimator/interpolator. Based on the comparison, the sampling rate for sampling the input signal with the processor can be set as part of the digital signal processing event. The sampling rate can be adjusted as the frequency of the input signal varies during the signal processing event.

A real time digital trigger detection channel includes an event detector, a pulse former, a low pass filter, an analog-to-digital converter (ADC) and a Discrete Fourier Transform (DFT) processor coupled in series. The event detector is responsive to an applied input signal and the presence of information requiring digital trigger generation. The pulse former generates a pre-determined, limited length, stable pulse signal which is applied to an anti-aliasing, pulse shaping low pass filter. The resultant shaped pulse signal is converted to a sequence of sample values by the ADC, which in turn are applied to the DFT processor, which in turn calculates a discrete Fourier transform of the output sequence of ADC samples, performing trigger position calculation based on values determined by the DFT processor.