Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.

A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

A confined data communication system includes a reference generation circuit operable to produce one or more analog reference signals, an analog to digital converter circuit operable to process an analog signal to produce a digital representative signal, a digital filtering circuit operable to filter the digital representative signal to produce an affect value, a data processing module operable to interpret the affect value to produce processed output data, and a processing module operable to set frequency and waveform for each of the one or more analog reference signals, set digital filtering parameters for the digital filtering circuit, set a sampling rate for the analog to digital converter circuit, and set data interpretation parameters for the data processing module.

An FIR filter-based filtering method and apparatus, a device, and a storage medium are provided. The FIR filter-based filtering method includes: acquiring a preset filtering order and a preset down-sampling multiple; selecting, according to the preset down-sampling multiple, a corresponding number of filter multiplexing units, and using each of the selected filter multiplexing units as a used filter multiplexing unit, wherein the FIR filter includes multiple filter multiplexing units; configuring, according to the preset filtering order, a filtering order for each used filter multiplexing unit; filtering, according to the preset down-sampling multiple, input data allocated to each used filter multiplexing unit through the each used filter multiplexing unit configured with the filtering order, to obtain unit filtered data outputted by the each used filter multiplexing unit; and merging the unit filtered data respectively outputted by the corresponding number of used filter multiplexing units and outputting merged unit filtered data.

A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

An interleaved cascaded integrator-comb (“CIC”) filter receives an interleaved sensor output signal, including a plurality of digitized sensor signals at an input clock rate. An integrator of the interleaved CIC filter processes the interleaved signal to output an integrated interleaved signal. A downsampler of the interleaved CIC filter buffers portions of the integrated interleaved corresponding to a decimation rate for the interleaved signal. The portions of the signals are provided to a comb filter, which outputs a decimated interleaved signal.

An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency. The analog signal includes a set of pure tone components. The first digital signal includes n 1-bit channels. The analog to digital conversion circuit further includes a digital decimation filtering circuit including n anti-aliasing filters operable to sample and filter the n 1-bit channels of the first digital signal to produce n second digital signals and n decimator circuits operable to decimate the n second digital signals to produce n third digital signals at a second data rate frequency. The analog to digital conversion circuit further includes a multiplexor operable to output the n third digital signals at the second data rate frequency on a single bus.

A Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity. The FIR filter includes a small number of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream. The MAC units are provided with coefficients from a memory. In an example implementation, the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.

Various exemplary embodiments are directed to methods including obtaining an input sample magnitude, filtering the obtained input sample magnitude, generating a sample-to-sample difference based on the filtered input sample magnitude, and engaging an actuator in accordance with a determination that the sample-to-sample difference satisfies a rate threshold. In addition, various exemplary embodiments are directed to devices including a processor, a control sensor operatively coupled to the processor and operable to obtain an input sample magnitude, an input filter operatively coupled to the processor and operable to filter the at least one obtained input magnitude sample, a non-transitory computer-readable medium operatively coupled to the processor and including a rate engine operable to generate a sample-to-sample difference based on the filtered input sample magnitude, and to generate a determination that the sample-to-sample difference satisfies a rate threshold, and a control actuator operatively coupled to the processor and operable to engage an operation mechanism in accordance with the determination that the sample-to-sample difference satisfies a rate threshold.

A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.