A method, an apparatus and a device for simultaneously sampling multiples signals and a medium are provided. The method includes: modulating multiple target input signals with CDM, to obtain a single target analog signal; performing ΔΣ modulation on the single target analog signal to obtain a target digital bit stream; demodulating the target digital bit stream to obtain a target demodulated bit stream; and filtering the target demodulated bit stream to obtain multiple target output signals. With the method, the hardware overhead for simultaneous sampling of multiple-channel signals is reduced while ensuring accuracy. Accordingly, the apparatus and the device, and the medium have the above beneficial effects.

An interleaved cascaded integrator-comb (“CIC”) filter receives an interleaved sensor output signal, including a plurality of digitized sensor signals at an input clock rate. An integrator of the interleaved CIC filter processes the interleaved signal to output an integrated interleaved signal. A downsampler of the interleaved CIC filter buffers portions of the integrated interleaved corresponding to a decimation rate for the interleaved signal. The portions of the signals are provided to a comb filter, which outputs a decimated interleaved signal.

In one aspect, a magnetic-field sensor includes main coil circuitry configured to generate a first magnetic-field signal at a first frequency; a first channel; a second channel; a subtractor circuit configured to subtract a second channel output signal from a first channel output signal to form a subtraction signal; an adder circuit configured to combine the first channel output signal and the second channel output signal to form a summation signal; processing circuitry configured to receive the summation signal and to provide a magnetic-field sensor output signal indicating a position of the target; feedback circuitry configured to receive the subtraction signal and to provide a first feedback signal to the processing circuitry, and a second feedback signal; and a secondary coil circuitry configured to receive the second feedback signal and to generate, based on the second feedback signal, a second magnetic-field signal to reduce the first magnetic-field signal received.

A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

A method for removing low frequency offset components from a digital data stream includes receiving, at an input of an analog-to-digital converter (ADC), an analog input signal from one or more analog front end components. The analog input signal has an associated low frequency offset due, at least in part, to the analog front end components. The method also includes generating, at an output of the ADC, a digital data stream representative of the analog input signal. The digital data stream having an associated low frequency offset due, at least in part, to the analog front end components and the ADC. One or more low pass finite impulse response (FIR) filters are applied to the digital data stream to detect the low frequency offset components in the digital data stream, and generate a filtered output signal with only the low frequency offset components present. A corrected digital data stream without the low frequency offset components is generated in response thereto, for example, by taking the difference of the filtered output signal from the digital data stream.

A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency f.sub.s, operate in accordance with a clock having a frequency f.sub.s×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency f.sub.D×M, decimates data at the sampling frequency f.sub.s input from the integration calculation unit (10) in the last stage at a sampling frequency f.sub.D, and delays data obtained as a result of decimation by (M−1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency f.sub.D×M, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samples before.

A device for signal processing includes a signal input, a control input, and a CIC filter of an nth order for filtering the input signal. The CIC filter includes n integrators, which are disposed one behind the other and include a memory in each case, and n is greater than one. For each of n−1 first integrators, the device includes an associated correction calculator for correcting an integration error using at least one signal value stored in the memory of the respective first integrator. The device transmits these stored signal values in response to the control signal to the associated correction calculators and to delete the memory of the remaining last integrator. Either the memories of the n−1 first integrators are also deleted, or the device includes a further correction calculator and the signal values are transmitted in response to the control signal also to the further correction calculator.

A finite impulse response (FIR) filter including a delay line and a plurality of arithmetic units. Each arithmetic unit is coupled to a different one of a plurality of tap points of the delay line, is configured to receive a respective signal value over the delay line, and is associated with a respective coefficient. Any given one of the arithmetic units is configured to receive a respective control word. The respective control word specifying: (i) a plurality of trivial multiplication operations, and (ii) a plurality of bit shift operations. Any given one of the arithmetic units is further configured to estimate or calculate a product of the respective signal of the arithmetic unit respective signal value and the respective coefficient of the arithmetic unit by performing the trivial multiplication operations and bit shift operations that are specified by the respective control word that is received at the given arithmetic unit.

The exemplary embodiments provide a parallel implementation of filters with recursive transfer functions. This can enable a filter to act as a frame filter that may process a frame of multiple samples of data in parallel rather than being limited to processing a single sample of data at a time. Each frame contains plural input samples of data values. The input samples are from a common source and have a time dependency. The exemplary embodiments are suitable for implementing various types of filters in parallel, such as cascaded integrator comb filters, biquad filters and other types of infinite impulse response (IIR) filters. The exemplary embodiments may use polyphase decomposition to decompose a filter with a recursive transfer function into multiple polyphase component filters. The polyphase component filters may be applied to respective samples of data in a parallel pipelined configuration to produce filtered output for the samples of data in parallel.

An analog-to-digital conversion system may include an analog-to-digital converter configured to convert an analog input signal into an equivalent digital input signal, a first filtering path configured to filter the equivalent digital input signal to generate a first filtered digital signal, wherein the first filtering path comprises a zero-overshoot monotonic step response filter, a second filtering path configured to filter the equivalent digital input signal to generate a second filtered digital signal, wherein the second filtering path comprises a frequency-selective filter; and a mixer configured to either: (i) select between the first filtered digital signal and the second filtered digital signal in order to generate an output digital signal; or (ii) combine selected proportions of each of the first filtered digital signal and the second filtered digital signal in order to generate the output digital signal.