An FIR filter-based filtering method and apparatus, a device, and a storage medium are provided. The FIR filter-based filtering method includes: acquiring a preset filtering order and a preset down-sampling multiple; selecting, according to the preset down-sampling multiple, a corresponding number of filter multiplexing units, and using each of the selected filter multiplexing units as a used filter multiplexing unit, wherein the FIR filter includes multiple filter multiplexing units; configuring, according to the preset filtering order, a filtering order for each used filter multiplexing unit; filtering, according to the preset down-sampling multiple, input data allocated to each used filter multiplexing unit through the each used filter multiplexing unit configured with the filtering order, to obtain unit filtered data outputted by the each used filter multiplexing unit; and merging the unit filtered data respectively outputted by the corresponding number of used filter multiplexing units and outputting merged unit filtered data.

Various exemplary embodiments are directed to methods including obtaining an input sample magnitude, filtering the obtained input sample magnitude, generating a sample-to-sample difference based on the filtered input sample magnitude, and engaging an actuator in accordance with a determination that the sample-to-sample difference satisfies a rate threshold. In addition, various exemplary embodiments are directed to devices including a processor, a control sensor operatively coupled to the processor and operable to obtain an input sample magnitude, an input filter operatively coupled to the processor and operable to filter the at least one obtained input magnitude sample, a non-transitory computer-readable medium operatively coupled to the processor and including a rate engine operable to generate a sample-to-sample difference based on the filtered input sample magnitude, and to generate a determination that the sample-to-sample difference satisfies a rate threshold, and a control actuator operatively coupled to the processor and operable to engage an operation mechanism in accordance with the determination that the sample-to-sample difference satisfies a rate threshold.

The sensor is configured to provide a digital output signal and has a digital detector, which is configured to detect a physical quantity and generate a conditioned digital signal indicative of the detected physical quantity; and a rate modification stage, configured to receive the conditioned digital signal and a group of parameters, the group of parameters comprising an interpolation factor and a downsampling factor, and to provide the digital output signal. The rate modification stage has an interpolator and a decimation element. The interpolator is configured to receive and to upsample the conditioned digital signal based on the interpolation factor and to provide an interpolated signal. The decimation element is configured to downsample the interpolated signal based on the downsampling factor, thereby generating the digital output signal.

Systems, devices, and methods related to a sample rate converter (SRC) for implementing a rate conversion R are provided. The SRC receives input samples at an input rate F.sub.in and outputs samples at an output rate F.sub.out=F.sub.in×R, where R is a fractional value greater than 1. The SRC includes a plurality of filters to process the received input samples and a multiplier-adder block to generate the output samples based on respective delta values and outputs of the plurality of filters. The SRC further includes a plurality of buffers to buffer samples between the plurality of filters and the multiplier-adder block based at least in part on N buffer read pointers, where N is an integer greater than 1. The SRC further includes resampler control circuitry to generate N delta values of the delta values and the N buffer read pointers in parallel based on R.

A method (500) for resampling an audio signal (110) is described. The method (500) comprising providing (501) a set of input subband signals (210) which is representative of a time domain audio signal. Furthermore, the method (500) comprises applying (502) a first ripple pre-emphasis gain (323) to a first input subband signal (210) of the set of input subband signals (210) to determine a corresponding first output subband signal (213) of a set of output subband signals (213). In addition, the method (500) comprises determining (503) a time domain input audio signal (110) from the set of output subband signals (213). The method (500) further comprises performing (504) time domain resampling of the input audio signal (110) to provide an output audio signal (113) using an anti-aliasing filter (102), wherein the first ripple pre-emphasis gain (323) is dependent on a frequency response (311) of the anti-aliasing filter (102), such that an amplitude ripple of the frequency response (311) of the anti-aliasing filter (102) is at least partially compensated by the first ripple pre-emphasis gain (323).

Embodiments of the present invention provide a digital signal processing apparatus, including an interpolator, an interpolating convolver, or the like, for providing a plurality of output samples or output values in parallel, such as P output samples provided by P Farrow cores, based on a set of input samples or input values, such as 2P+M−2 samples. The digital signal processing apparatus includes a sample distribution logic or structure configured to provide a plurality of subsets of the set of input samples to a plurality of processing cores, such as interpolation cores (e.g., Farrow cores) that perform processing operations associated with different time shifts, for example with respect to a reference time (e.g., a time associated with the input samples). The sample distribution logic includes a hierarchical tree structure having a plurality of hierarchical levels of splitting nodes.

Embodiments of the present invention provide a digital signal processing apparatus including a combiner logic and a plurality of processing cores. Input samples of the digital signal processing apparatus are provided to the plurality of processing cores. Sets of output samples of the processing cores are provided to the combiner logic as input samples, and the sets of samples are provided to the combiner nodes c of the highest hierarchical level (h=0). A digital signal processing apparatus or a parallel decimating digital convolver may be used as a building block of a signal processor application-specific integrated circuit (ASIC) and/or part of other instruments for generating output samples. Furthermore, applications of the digital signal processing apparatus described herein can be addressed on a parallel DSP, in a response time of real-time or near to real-time, for flexible (or almost arbitrary high) sample rates.

Disclosed are an audio rate conversion system and an electronic apparatus. The audio rate conversion system includes an integrator-comb filter, a multi-rate filter and a first half-band filter, an input of the integrator-comb filter being accessed with digital audio data, an output of the integrator-comb filter being sequentially connected to the multi-rate filter and the first half-band filter; where, the integrator-comb filter is configured to reduce a rate of the digital audio data according to a preset decimation rate; the multi-rate filter is configured to convert a rate of digital audio data output by the integrator-comb filter into a rate of digital audio data corresponding to an accessed control signal according to the control signal; and the first half-band filter is configured to reduce a rate of digital audio data output by the multi-rate filter.

A digital signal processor is designed to channelize an input signal, and includes a channelizer circuit and a plurality of tuning modules. The channelizer circuit is designed to receive an input signal having a first bandwidth and to channelize the input signal into a first set of channels each having a bandwidth smaller than the first bandwidth as a first output signal and to channelize the input signal into a second set of channels having a bandwidth smaller than the first bandwidth as a second output signal. The plurality of tuning modules are designed to receive one or more channels from the first output signal or the second output signal and to further downsample the one or more channels to a user-defined bandwidth at a user-defined center frequency. Each of the plurality of tuning modules include a plurality of FIR filter blocks and a memory having a plurality of FIR filter coefficients.

One example includes a digital signal conditioner (DSC) system. A sample selector bank receives a digital sample block of an input signal that is provided at a supported input oversampling factor and selects a subset of samples from the digital sample block based on a selection signal. A tap weights selector bank generates a set of tap weights based on the selection signal. A filter bank receives the subset of the samples from each of the sample selectors and a respective set of tap weights. Each filter provides a weighted sample associated with the respective subset of samples and the respective set of tap weights. A reformattor receives the weighted sample from each of the filters and provides a filtered sample block including the weighted sample from a subset of the filters at an output oversampling factor for each supported input oversampling factor based on a selected supported resampling ratio.