Dual mode filters having two reconfigurable multi-stage filters. In a dual band mode, each reconfigurable filter filters an input signal in a different band using every filter stage. In a single band mode, both reconfigurable filters are effectively divided into two sub-chains that include either the odd-numbered filter stages or the even-numbered filter stages. Together, the four sub-chains in the single band mode filter an input signal in a single band with a higher parallelization than each reconfigurable filter in the dual band mode. In some embodiments, the dual mode filter is a decimation filter. In other embodiments, the dual mode filter is a resampling filter. In still other embodiments, the dual mode filter is an interpolation filter.

A digital filter circuit for filtering at least two input signals having different signal data rates is described. The digital filter circuit includes an input multiplexer sub-circuit, a digital filter, and an output multiplexer sub-circuit. The digital filter is connected to the input multiplexer sub-circuit downstream of the input multiplexer sub-circuit. The digital filter is connected to the output multiplexer sub-circuit upstream of the output multiplexer sub-circuit. The input multiplexer sub-circuit is configured to receive the at least two input signals having different signal data rates. The input multiplexer sub-circuit is configured to selectively forward the at least two input signals to the digital filter. The digital filter is configured to filter the at least two input signals, thereby obtaining at least two filtered input signals. The output multiplexer sub-circuit is configured to selectively output the at least two filtered input signals. Further, a measurement instrument and a signal processing method are described.

There is provided mechanisms for enabling linearization of a non-linear electronic device. A method is performed by a linearizer device. The method comprises receiving an input signal destined to be input to the non-linear electronic device. Input-output characteristics of the non-linear electronic device is represented by a model. The model is defined by a mathematical expression, and wherein input-output characteristics of the linearizer device is given by the linearization function. The linearization function is determined by applying a function recursion to the mathematical expression of the model. The method comprises obtaining an output signal by subjecting the input signal to the linearization function. The method comprises providing the output signal, instead of the input signal, as input to the non-linear electronic device, thereby enabling linearization of the non-linear electronic device.

An FIR filter-based filtering method and apparatus, a device, and a storage medium are provided. The FIR filter-based filtering method includes: acquiring a preset filtering order and a preset down-sampling multiple; selecting, according to the preset down-sampling multiple, a corresponding number of filter multiplexing units, and using each of the selected filter multiplexing units as a used filter multiplexing unit, wherein the FIR filter includes multiple filter multiplexing units; configuring, according to the preset filtering order, a filtering order for each used filter multiplexing unit; filtering, according to the preset down-sampling multiple, input data allocated to each used filter multiplexing unit through the each used filter multiplexing unit configured with the filtering order, to obtain unit filtered data outputted by the each used filter multiplexing unit; and merging the unit filtered data respectively outputted by the corresponding number of used filter multiplexing units and outputting merged unit filtered data.

Systems and methods for producing a linear-phase digital FIR filter from two sub-filters for an audio signal. In one method, the sub-filters are provided as sub-sets having numbers of coefficients, a lower cutoff frequency of the particular sub-filter being greater than the sampling frequency of the audio signal divided by the number. The sub-sets are linearly convoluted with one another so as to form a total set having a number of coefficients greater than the numbers, and the total set is symmetrically reduced to a number less than the number, so as to form a reduced total set of the filter. A linear-phase digital FIR filter for an audio signal is created by the method.

A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.

A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.

A finite impulse response (FIR) filter including an input of the FIR filter that receives an RF input signal, a clock input configured to receive a clock signal, an output of the FIR filter that provides a filtered output signal, a plurality of signal paths including a plurality of sample-and-hold circuits and a plurality of multipliers arranged in parallel, each signal path including a respective sample-and-hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal, and a controller.

A Finite Impulse Response (FIR) filter that reduces the complexity of the hardware required for a filter with a high decimation factor while achieving similar performance of prior art poly-phase filters of greater complexity. The FIR filter includes a small number of multiply-and-accumulate (MAC) units connected in parallel to each other between an input stream and an output stream. The MAC units are provided with coefficients from a memory. In an example implementation, the memory is addressed by a counter and the output of the memory selected by a multiplexer for suppling the coefficients.

An inverter system for mitigating oscillation of an electric motor that drives a load comprises a torque command generation module for receiving a commanded torque from an operator of a vehicle. A torque damping module is configured to receive the commanded torque and generating a commanded compensating torque to dampen any mechanical oscillation or resonance of the electric motor based on the observed rotational speed of the motor. The torque damping module further comprises a digital filter of order greater than one, a gain adjuster and a limiter.