Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption.

Biquad stage systems and methods include receiving at biquad sections a signal sample, generating, by each biquad section, a pair of output values based on the signal sample, including a first value based on fixed-point processing path and a second value emulating a floating-point processing path, and accumulating the pair of output values from each of the plurality of biquad sections to generate an output signal. The biquad stage receives an N-bit input signal, which is processed by a biquad section. Delay elements delay the signal sample before input to other biquad sections. The delayed signal sample is input to the first processing path and the second processing path of a corresponding biquad stage. By performing the processing based on two paths, a more accurate result can be found when using a reduced word length in the multiply operations resulting in a lowering of the power consumption.

Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.

Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.

Methods and devices for switching filters and medical apparatuses using the same are described. The method includes: detecting whether or not a frequency range of an input signal is changed from a first frequency range into a second frequency range; if changed, switching from a first filter to a second filter, and taking a sample value of the input signal at a current moment as an input value of the second filter at the current moment and sample values of the input signal at n moments before the current moment as input values of the second filter at the n moments, respectively, and taking output values of the first filter at m moments before the current moment as output values of the second filter at the m moments, to obtain an output value of the second filter at the current moment.