In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.

Methods and apparatus are provided for adapting gain elements in digital filter chains. In one example, a digital filter chain includes a first digital filter and a second digital filter having an input coupled to an output of the first digital filter. A common gain is applied to signal samples passing between the first digital filter and the second digital filter, the common gain corresponding to a product of an output gain associated with the first digital filter and an input gain associated with the second digital filter. In another example, a digital filter includes an adjustable input gain element and an adjustable output gain element. The adjustable input gain element is configured to apply a gain value to an input signal sample, the gain value comprising a resultant difference of a bitshift configured for the digital filter and a bitwidth extension value. The adjustable output gain element is configured to apply an opposite of the gain value to an output signal sample.

The present disclosure describes methods, systems, and computer program products for a reducing crest factors. An input signal is received. The input signal includes a clipping signal that reduces a peak amplitude of a source signal based on a predetermined clipping level. The input signal is transposed to a plurality of transposed signals using a plurality of multipliers. A feedback signal is generated based on the plurality of transposed signals using a first plurality of delay taps. A windowing signal is generated based on the feedback signal. The windowing signal is used to reduce a crest factor of the source signal.

Methods and apparatus are provided for adapting gain elements in digital filter chains. In one example, a digital filter chain includes a first digital filter and a second digital filter having an input coupled to an output of the first digital filter. A common gain is applied to signal samples passing between the first digital filter and the second digital filter, the common gain corresponding to a product of an output gain associated with the first digital filter and an input gain associated with the second digital filter. In another example, a digital filter includes an adjustable input gain element and an adjustable output gain element. The adjustable input gain element is configured to apply a gain value to an input signal sample, the gain value comprising a resultant difference of a bitshift configured for the digital filter and a bitwidth extension value. The adjustable output gain element is configured to apply an opposite of the gain value to an output signal sample.

Methods and apparatus are provided for adapting gain elements in digital filter chains. In one example, a digital filter chain includes a first digital filter and a second digital filter. The first digital filter includes a fixed point finite impulse response (FIR) filter and includes an output gain element. The second digital filter has an input coupled to an output of the first digital filter and includes an IIR filter. The output gain element applies a common output gain value that is based on a product of an input gain configured in association with the second digital filter and an FIR output gain that is based on a scaling factor K associated with the first digital filter.

The present disclosure describes methods, systems, and computer program products for a reducing crest factors. An input signal is received. The input signal includes a clipping signal that reduces a peak amplitude of a source signal based on a predetermined clipping level. The input signal is transposed to a plurality of transposed signals using a plurality of multipliers. A feedback signal is generated based on the plurality of transposed signals using a first plurality of delay taps. A windowing signal is generated based on the feedback signal. The windowing signal is used to reduce a crest factor of the source signal.

The present disclosure provides implementations of a filter suitable for use in quantum computing systems and other low-power, high-speed applications. In some aspects, a filter circuit includes a series-connected arrangement of unit delays and summers in an alternating pattern. The filter circuit further includes a plurality of coefficient multipliers, each having a respective output connected with one or more of the summers, and each including a multiplexing stage including one or more multiplexers addressed using one or more bits of a respective input coefficient vector. A first coefficient multiplier of the plurality of coefficient multipliers includes a partial product stage configured to provide a plurality of integer partial products of an input data vector to the multiplexing stages of the plurality of coefficient multipliers.