According to one embodiment, in a biquad filter, an output terminal of a first integrator is connected to an input terminal in a negative pole side of a second integrator, an output terminal of the first integrator is connected to a first input terminal in a negative pole side of an adder through the inversion amplifier, an output terminal of the second integrator is connected to a second input terminal in the negative pole side of the adder, an input terminal to which an input signal is input is connected to a third input terminal in the negative side of the adder, and an output terminal of the adder is connected to an input terminal in a negative pole side of the first integrator.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

Self-interference cancellers are provided. The self-interference cancellers can include multiple second-order, N-path G.sub.m-C filters. Each filter can be configured to cancel self-interference on a channel of a desired bandwidth. Each filter can be independently controlled using a variable transmitter resistance, a variable receiver resistance, a variable baseband capacitance, a variable transconductance, and a variable time shift between local oscillators that control switches in the filter. By controlling these variables, magnitude, phase, slope of magnitude, and slope of phase of the cancellers frequency responses can be controlled for self-interference cancellation. A calibration process is also provided for configuring the canceller.

A method and apparatus for modifying or controlling a resonator connected to a signal loop having an input, an output, and a closed loop frequency response. The signal loop has a primary resonator having a primary frequency response. There is at least one adjustable resonator having an adjustable frequency and a secondary Q-factor. An adjustable scaling block applies a gain factor. A controller is connected to the at least one adjustable resonator and the adjustable scaling block. The controller has instructions to adjust the closed loop frequency response toward a desired closed loop frequency response by controlling the adjustable frequency of the at least one adjustable resonator and the gain factor of the adjustable scaling block.

A method and apparatus for modifying or controlling a resonator connected to a signal loop having an input (18828), an output (18822), and a closed loop frequency response. The signal loop has a primary resonator (18810) having a primary frequency response. There is at least one adjustable resonator (18812) having an adjustable frequency (f) and a secondary Q-factor. An adjustable scaling block (18824) applies a gain factor (g). A controller is connected to the at least one adjustable resonator (18812) and the adjustable scaling block (18824). The controller has instructions to adjust the closed loop frequency response toward a desired closed loop frequency response by controlling the adjustable frequency (f) of the at least one adjustable resonator (18812) and the gain factor (g) of the adjustable scaling block (18824).

According to one embodiment, in a biquad filter, an output terminal of a first integrator is connected to an input terminal in a negative pole side of a second integrator, an output terminal of the first integrator is connected to a first input terminal in a negative pole side of an adder through the inversion amplifier, an output terminal of the second integrator is connected to a second input terminal in the negative pole side of the adder, an input terminal to which an input signal is input is connected to a third input terminal in the negative side of the adder, and an output terminal of the adder is connected to an input terminal in a negative pole side of the first integrator.

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2.sup.n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

Embodiments of methods and systems for attenuator phase compensation are described. In an embodiment, a method for attenuator phase compensation involves determining a phase compensation value for an attenuator based on an attenuation configuration of the attenuator and performing phase compensation according to the phase compensation value to maintain a constant phase response.