Patent classifications
H03H7/24
Apparatuses And Methods For Signal Coupling
Coupling apparatuses, circuits having such coupling apparatuses and corresponding methods are provided that involve a first and a second signal being coupled out from an out-coupling circuit part and being separately coupled into first and second circuit pmts. The use of different coupling mechanisms effects signal separation in this case. In particular, one of the signals can be coupled as a differential signal and the other as a common mode signal.
Apparatuses And Methods For Signal Coupling
Coupling apparatuses, circuits having such coupling apparatuses and corresponding methods are provided that involve a first and a second signal being coupled out from an out-coupling circuit part and being separately coupled into first and second circuit pmts. The use of different coupling mechanisms effects signal separation in this case. In particular, one of the signals can be coupled as a differential signal and the other as a common mode signal.
Method and Apparatus to Optimize Power Clamping
A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
Method and Apparatus to Optimize Power Clamping
A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
Apparatus for monitoring pulsed high-frequency power and substrate processing apparatus including the same
Disclosed are an apparatus for monitoring pulsed high-frequency power and a substrate processing apparatus including the same. The apparatus includes an attenuation module configured to attenuate a pulsed high-frequency power signal; a rectifier module configured to convert the pulsed high-frequency power signal into a direct current signal; and a detection module configured to detect a pulse parameter based on the direct current signal.
Apparatus for monitoring pulsed high-frequency power and substrate processing apparatus including the same
Disclosed are an apparatus for monitoring pulsed high-frequency power and a substrate processing apparatus including the same. The apparatus includes an attenuation module configured to attenuate a pulsed high-frequency power signal; a rectifier module configured to convert the pulsed high-frequency power signal into a direct current signal; and a detection module configured to detect a pulse parameter based on the direct current signal.
Multiscale vector constellation
An attenuator is configured to attenuate and phase-shift a radiofrequency signal according to a control signal, having a plurality of first attenuation cells (A.sub.1, A.sub.N−1), configured to attenuate said radiofrequency signal by a predetermined value and activated according to a particular bit of the control signal, and implementing a combinatorial logic on the bits of the control signal that are used to control the first attenuation cells, and at least one second attenuation cell (B.sub.1, B.sub.M) configured to attenuate said radiofrequency signal by a predetermined value and activated according to a particular output implementing the combinatorial logic. A control node is also provided for an array antenna having such an attenuator, and an array antenna having an array of such control node and a satellite.
WIDEBAND SIGNAL ATTENUATOR
Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state (“enabled”) or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.
WIDEBAND SIGNAL ATTENUATOR
Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state (“enabled”) or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.
Voltage-divider circuits and circuitry
A voltage-divider circuit, including: a network of discrete resistors defining T tiers of resistors, where T≥2, the T tiers comprising first and subsequent tiers, the Xth tier including at least one Xth-tier resistor where X=1, and the Xth tier including at least two Xth-tier resistors for each value of X in the range 2≤X≤T, wherein, for each value of X in the range 1≤X<T: each Xth-tier resistor is connected between a pair of nodes of the voltage-divider circuit at which a relatively high and low voltage signal are provided, respectively; at least one Xth-tier resistor is implemented as a subdivision network of discrete resistors; and for each Xth-tier resistor implemented as a subdivision network, that subdivision network includes a main resistor connected in series with a corresponding auxiliary resistor, that main resistor implemented as a base resistor connected in parallel with a series connection of a plurality of X+1th-tier resistors.