An RF integrated circuit device can includes a substrate and a High Electron Mobility Transistor (HEMT) device on the substrate including a ScAlN layer configured to provide a buffer layer of the HEMT device to confine formation of a 2DEG channel region of the HEMT device. An RF piezoelectric resonator device can be on the substrate including the ScAlN layer sandwiched between a top electrode and a bottom electrode of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.

A bulk acoustic wave filter, a manufacturing method thereof, and a communication device are disclosed. The bulk acoustic wave filter includes a first filter substrate and a second filter substrate; the first filter substrate includes a first base substrate and a first resonator, a first electrode pad and a first auxiliary pad arranged on the first base substrate; the second filter substrate includes a second base substrate and a second resonator, a second electrode pad and a second auxiliary pad arranged on the second base substrate, the first filter substrate is arranged opposite to the second filter substrate, the first electrode pad and the second auxiliary pad are in contact with each other, and the second electrode pad and the first auxiliary pad are in contact with each other.

The present disclosure provides a radio frequency filter, including: a substrate; a supporting electrode protruded on a front surface of the substrate; and a thin film structure formed on the substrate and spaced with the substrate by the supporting electrode. An end surface of a top end of the supporting electrode is in sealing contact with a front surface of the thin film structure.

A high-frequency apparatus includes a resin substrate, a first device including a substrate and provided on the resin substrate, and a second device provided adjacent to the first device on the resin substrate. Each of the first device and the second device includes an acoustic wave device. The second device includes a piezoelectric substrate and a functional element provided on the piezoelectric substrate. The substrate of the first device includes Si or a laminated material including Si. The piezoelectric substrate of the second device includes LiTaO.sub.3, LiNbO.sub.3, or a laminated material including LiTaO.sub.3 or LiNbO.sub.3. The resin substrate includes glass.

An electronic component includes: a first substrate having a first surface; a second substrate having a second surface facing the first surface across an air gap; a first coil pattern that is located on the first surface so as to face the second surface across the air gap; a second coil pattern that is located in a second region on the second surface and faces the first surface across the air gap, at least a part of the second region overlapping with a first region in plan view, the first region being formed of a region in which the first coil pattern is located and a region surrounded by the first coil pattern; and a connection terminal connecting the first coil pattern and the second coil pattern.

The present disclosure provides a package structure of an air gap type semiconductor device and its fabrication method. The fabrication method includes forming a bonding layer having a first opening on a carrier; disposing a semiconductor chip on the bonding layer, thereby forming a first cavity at the first opening, where the first cavity is at least aligned with a portion of an active region of the semiconductor chip; performing an encapsulation process to encapsulate the semiconductor chip on the carrier; lastly, forming through holes passing through the carrier where each through hole is aligned with a corresponding input/output electrode region of the semiconductor chip, and forming interconnection structures on a side of the carrier different from a side with the bonding layer, where each interconnection structure passes through a corresponding through hole and is electrically connected to an corresponding input/output electrode.

Techniques regarding forming flip chip interconnects are provided. For example, one or more embodiments described herein can comprise a three-dimensionally printed flip chip interconnect that includes an electrically conductive ink material that is compatible with a three-dimensional printing technology. The three-dimensionally printed flip chip interconnect can be located on a metal surface of a semiconductor chip.

An acoustic resonator device with low thermal impedance has a substrate and a single-crystal piezoelectric plate having a back surface attached to a top surface of the substrate via a bonding oxide (BOX) layer. An interdigital transducer (IDT) formed on the front surface of the plate has interleaved fingers disposed on the diaphragm, the overlapping distance of the interleaved fingers defining an aperture of the resonator device. Contact pads are formed at selected locations over the surface of the substrate to provide electrical connections between the IDT and contact bumps to be attached to the contact pads. The piezoelectric plate is removed from at least a portion of the surface area of the device beneath each of the contact pads to provide lower thermal resistance between the contact bumps and the substrate.

In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

An electronic component housing package includes: an insulating substrate including a main surface; an external connection conductor including a portion exposed at the main surface; and an inner layer conductor located inside of the external connection conductor in a thickness direction of the insulating substrate, in which the external connection conductor includes a protruding portion extending toward the inner layer conductor, and the protruding portion is in contact with the inner layer conductor.