The disclosure relates to a pulsed laser driver that utilizes a high-voltage switch transistor to support a high output voltage for a laser, and a low-voltage switch transistor that switches between an ON state and an OFF state to generate a pulsed current that is supplied to the laser to generate an output pulsed laser signal. The pulsed laser driver switches the low-voltage switch transistor between the ON state and the OFF state according to an input pulsed signal such that the output pulsed laser signal is modulated according to the input pulsed signal. The pulsed laser driver also utilizes a feedback control module to control the gate terminal voltage of the high-voltage switch transistor to improve the precision of the output pulsed laser signal.

A change rate control circuit computes a first drive speed, which is a gate drive speed of a gate of a drive-subject element, for controlling a change rate of an element voltage of the drive-subject element at a target change rate during a change period. A timing generating circuit acquires, in advance, a delay time caused when the gate is driven and determines a switching timing, at which the element voltage reaches a switching threshold voltage which is lower than a desired switching voltage by a predetermined value, during turn-off of the drive-subject element and generates a timing signal representing the switching timing. A speed change circuit changes the gate drive speed from the first drive speed to a second drive speed at the switching timing during turn-off of the drive-subject element.

A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.

A bootstrap circuit supporting fast charging and discharging and a chip. A voltage measurement module (12) and a switch module (11) are arranged, and the voltage measurement module (12) controls an operating state of the switch module (11); during charging, under a specific condition, the switch module (11) is enabled to be in an on state so as to achieve fast charging of a voltage output end; and during discharging, the purpose of fast discharging is achieved by means of a second field effect transistor (MP5) arranged in the bootstrap circuit.

A gallium nitride (GaN) device, where a drain of the GaN device includes a p-type (P-GaN) layer and a drain metal. The drain metal includes a plurality of first structural intervals and a plurality of second structural intervals. The plurality of first structural intervals and the plurality of second structural intervals are alternately distributed in the gate width direction. In this way, the drain metal implements local injection of holes for the device in the first structural intervals, and forms ohmic contact in the second structural intervals, implementing current conduction from a drain to a source of the device.

The present description concerns a method of controlling at least one switch (TH), including: the reception of signals (S3-i) having between one another at least one phase shift representative of a desired state of said at least one switch; the obtaining, from said signals, of a value (Si) representative of the desired state; and the application of the representative value to said at least one switch.

The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.

A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.

Passive gate bias network topologies are implemented for stacked FET switch structures, which improve the settling time and low cut-off frequency for both DC and non-DC operation. DC capable stacked switch bias structures provide gate and bulk bias voltages, using input DC voltages, which are coupled to the gate terminals and the bulk terminals of the stacked switches. The DC coupling can be achieved using resistors, or a combination of resistors and diodes. An exemplary SPST switch includes a series stacked switch in combination with a shunt stacked switch, which can be controlled between alternating states. For low cut-off frequency improvement structures, an input signal is coupled to the gate terminals and bulk terminals of the switches in the stacked switches, using a DC block capacitor and resistors. The low cut-off of the bulk can be improved by connecting the bulk terminal of one switch to the opposite polarity switch.

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.