A semiconductor device including: NMOS transistors respectively having the drains, which are connectable to respective second terminals of boot capacitors of which respective first terminals are connectable to respective nodes at which high-side transistors and the low-side transistors are connected together, and the sources, which are electrically connectable to an application terminal for a supply voltage; and controllers driving respective gates of the plurality of NMOS transistors. When the high-side transistor for a first channel is kept off by the driver for the first channel, the high-side transistor for a second channel, which is different from the first channel, is kept on by the driver for the second channel. The controller for the first channel feeds a drive voltage based on the boot voltage for the second channel to the gate of the NMOS transistor for the first channel to keep on the NMOS transistor.

A gate driver device includes a first field effect transistor and a first driver circuit. The first field effect transistor includes a first gate electrode and a first backgate structure. The first driver circuit supplies a first backgate drive signal to the first backgate structure.

A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

There is provided an apparatus and method, the apparatus comprising a power input and a switch isolation circuit to provide isolation between the power input and a protected switch responsive to a timing signal. The switch isolation circuit comprises a switch isolation charge store, and a buffer circuit to receive power from the switch isolation charge store and coupled between the timing signal and the protected switch. The switch isolation circuit is configured to, in response to the timing signal having the first value, operate in a powered mode in which the switch isolation charge store receives power from the power input; and, in response to the timing signal having the second value, operate in an isolation mode in which the switch isolation charge store is isolated from the power input.

A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.

A switched current source circuit, comprising first and second voltage source nodes; a load; a current source; and capacitor switching circuitry comprising a load node, a capacitor and a plurality of switches configured, based on a control signal, to adopt a biasing configuration followed by an active configuration, wherein in the biasing configuration, the load node is conductively connected to the second voltage source node to bias a voltage level at the load node, and the capacitor is connected so that it at least partly charges; and in the active configuration, the load node is conductively connected via the load to the first voltage source node, and via the capacitor to the current source to increase a potential difference between the first voltage source node and the load node.

A switched current source circuit, comprising first and second voltage source nodes; a load; a current source; and capacitor switching circuitry comprising a load node, a capacitor and a plurality of switches configured, based on a control signal, to adopt a biasing configuration followed by an active configuration, wherein in the biasing configuration, the load node is conductively connected to the second voltage source node to bias a voltage level at the load node, and the capacitor is connected so that it at least partly charges; and in the active configuration, the load node is conductively connected via the load to the first voltage source node, and via the capacitor to the current source to increase a potential difference between the first voltage source node and the load node.

This application discloses a drive circuit of a bridge arm switching transistor, a drive circuit, and a power converter. The bridge arm switching transistor includes a first switching transistor and a second switching transistor. A first terminal of the first switching transistor is connected to a power supply, a second terminal of the first switching transistor is connected to a first terminal of the second switching transistor, and a second terminal of the second switching transistor is grounded. The drive circuit includes a low-voltage region and at least two high-voltage regions isolated which include a first high-voltage region and a second high-voltage region. A semiconductor device configured to drive the second switching transistor is disposed in the low-voltage region. P-type semiconductor devices are disposed in each of the first high-voltage region and the second high-voltage region, and the P-type semiconductor devices are configured to drive the first switching transistor.

This application discloses a drive circuit of a bridge arm switching transistor, a drive circuit, and a power converter. The bridge arm switching transistor includes a first switching transistor and a second switching transistor. A first terminal of the first switching transistor is connected to a power supply, a second terminal of the first switching transistor is connected to a first terminal of the second switching transistor, and a second terminal of the second switching transistor is grounded. The drive circuit includes a low-voltage region and at least two high-voltage regions isolated which include a first high-voltage region and a second high-voltage region. A semiconductor device configured to drive the second switching transistor is disposed in the low-voltage region. P-type semiconductor devices are disposed in each of the first high-voltage region and the second high-voltage region, and the P-type semiconductor devices are configured to drive the first switching transistor.

A change rate control circuit computes a first drive speed, which is a gate drive speed of a gate of a drive-subject element, for controlling a change rate of an element voltage of the drive-subject element at a target change rate during a change period. A timing generating circuit acquires, in advance, a delay time caused when the gate is driven and determines a switching timing, at which the element voltage reaches a switching threshold voltage which is lower than a desired switching voltage by a predetermined value, during turn-off of the drive-subject element and generates a timing signal representing the switching timing. A speed change circuit changes the gate drive speed from the first drive speed to a second drive speed at the switching timing during turn-off of the drive-subject element.