Disclosed is a semiconductor integrated circuit for a regulator for forming a low current consumption type DC power supply device. The semiconductor integrated circuit includes an output transistor, a control circuit, an operation control transistor and a soft start circuit. The output transistor is connected between an output terminal and a voltage input terminal to which a DC voltage is input. The control circuit controls the output transistor according to a feedback voltage of an output. The operation control transistor controls an operation state of the control circuit. The soft start circuit gradually changes a voltage applied to a control terminal of the operation control transistor and delays activation of the control circuit at a time of applying a power supply voltage to the voltage input terminal.

Provided is a transistor drive circuit that drives a transistor to be driven and has a configuration including a controller that performs control to cause to temporally vary a circuit parameter contributing to a rise time or a fall time of the transistor to be driven.

An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

The present invention provides a drive device and a power supply system capable of driving a power transistor with low power while reflecting variations in manufacture process and external environments. A trigger detection circuit monitors a voltage between terminals or a current between terminals in a switching period of a power transistor and detects that the voltage between terminals or the current between terminals reaches a predetermined reference value. A current switching circuit selects a register outputting a current value to a variable current driver circuit from a plurality of registers and switches the register to be selected using a detection result of the trigger detection circuit as a trigger in the switching period, thereby making the drive current of the variable current driver circuit shift.

Methods, apparatus, systems and articles of manufacture are described to parallelize transistors. An example apparatus includes a first transistor on a first die and a second transistor on a second die. The example apparatus includes a parallel feedback terminal coupled to the first die and the second die and a current sensor including a first contact and a second contact. The example apparatus includes a resistor coupled to the current sensor and at least one of the switched terminal or a ground terminal. The example apparatus includes an active drive controller including a first input coupled to the resistor, a second input coupled to the parallel feedback terminal, and an output coupled to the parallel feedback terminal. The example apparatus includes an edge delay controller adapted to be coupled to a gate driver and an error amplifier, and a control contact adapted to be coupled to the gate driver.

An electronic circuit includes: a bus bar connected to a power source having a positive terminal and a negative terminal; and a plurality of object switching elements as driving objects connected to the bus bar, the object switching elements forming a parallel connected circuit. The object switching elements include minimum on-resistance elements having minimum on-resistance compared to other object switching elements in a corresponding current region among mutually different current regions; and connection points between the minimum on-resistance elements and the bus bar are located at different locations to have mutually different inductance of respective conduction paths between the power source to the connection points located at the different locations.

A drive device for controlling a power switching element includes: an on-side circuit that performs an on operation of the power switching element; and an off-side circuit that performs an off operation of the power switching element. The on-side circuit or the off-side circuit includes: multiple main MOS transistors; a sense MOS transistor that define a drain current of each main MOS transistor; and a sense current control circuit that controls a drain current of the sense MOS transistor to be constant; and a switch circuit that is connected to the gate of each main MOS transistor, and controls each main MOS transistor to turn on and off so as to switch a gate current in the power switching element.

In accordance with an embodiment, a method of driving a switching transistor includes receiving an activation signal for the switching transistor and generating a sequence of random values. Upon receipt of the activation signal, a control node of the switching transistor is driven with a drive strength based on a random value of the sequence of random values.

A circuit and method for digital controlling the slew rate of load voltage are provided. The circuit is comprised of a digital slew-rate control unit that utilizes a feedback signal to generate control signals where the feedback signal indicates the observed rate of voltage change on the load. The circuit is further comprised of a load driver circuit that is operated by the control signals and provides a slew-rate controlled output voltage used to operate a load switch, where the load switch provides power to the load. The circuit is configured to operate the load switch using a slew-rate controlling driver, depending on the state of the load switch transition, and a non-controlling driver.