A method and apparatus are provided for controlling a drive terminal of a power transistor by applying a turn-off voltage to the drive terminal at a turn-off time, measuring a gate current at the drive terminal to detect a predetermined gate current slope, determining a first time increment after the turn-off time when the predetermined gate current slope is detected, determining a second time increment which is proportional to the first time increment and which expires within a Miller plateau for the power transistor, and lowering the gate current at the drive terminal to a predetermined current level upon expiration of the second time increment in order to reduce overvoltages at the power transistor.

An electric power converter includes an electric gatedriver circuit that includes a transformer. The transformer includes separate first and second cores of magnetically conductive material that are shaped to form respective closed loops. The transformer also includes a first electrical conductor with at least one winding arranged around a part of the first core in a first winding direction and at least one winding arranged around a part of the second core in a second winding direction opposite the first winding direction. The transformer further includes a second electrical conductor with at least one winding arranged around a part of the first core in the first winding direction and at least one winding arranged around a part of the second core in the second winding direction so as to counteract electric influence induced by a common magnetic field through the closed loops of the first and second cores.

A control circuit of a power conversion apparatus is provided with a switch driving unit that drives the upper and lower arm switches; a short circuit control unit that causes the switch driving unit to execute a short circuit control when a failure occurs in the system, the short circuit control turning an ON side switch to an ON state and turning an OFF side switch to an OFF state; a checking unit that executes a checking process to check whether the short circuit control is able to perform correctly; and a protection control unit that causes the switch driving unit to execute a protection control when a failure occurs on either the upper arm switch or the lower arm switch, the protection control turning the switch where the failure occurs to an OFF state. The control circuit enables the protection control during execution of the checking process.

A power chip includes: a first power switch, formed in a wafer region and having a first and a second metal electrodes; a second power switch, formed in the wafer region and having a third and a fourth metal electrodes, wherein the first and second power switches respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, and the first and second power switches are alternately arranged; and a metal region, at least including a first metal layer and a second metal layer that are stacked, each metal layer including a first to a third electrodes, and electrodes with the same voltage potential in the metal layers are electrically coupled.

A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.

A load control device for controlling power delivered from an alternating-current power source to an electrical load may comprise a controllably conductive device, a control circuit, and an overcurrent protection circuit that is configured to be disabled when the controllably conductive device is non-conductive. The control circuit may be configured to control the controllably conductive device to be non-conductive at the beginning of each half-cycle of the AC power source and to render the controllably conductive device conductive at a firing time during each half-cycle (e.g., using a forward phase-control dimming technique). The overcurrent protection circuit may be configured to render the controllably conductive device non-conductive in the event of an overcurrent condition in the controllably conductive device. The overcurrent protection circuit may be disabled when the controllably conductive device is non-conductive and enabled after the firing time when the controllably conductive device is rendered conductive during each half-cycle.

A semiconductor device includes high-side and low-side switching elements connected in series to form a switching arm, a high-side driver IC for driving the high-side switching element, and, on a chip separate from the high-side switching element, a low-side driver IC for driving the low-side switching element. The driver IC includes a first controller for monitoring a switching voltage appearing at the node where the high-side and low-side switching elements are connected together. When a first driving control signal fed in from outside the semiconductor device instructs to turn on the high-side switching element, the first controller determines whether or not to permit the high-side switching element to be turned on based on a result of checking the switching voltage.

A drive circuit of a power semiconductor element comprises a gate drive voltage generator to generate, based on an ON/OFF drive timing signal input to an input terminal, a gate drive voltage to be applied to a gate electrode of a switching element having the gate electrode for controlling a main current that flows between a first main electrode and a second main electrode, wherein the gate drive voltage generator includes a gate current limiting circuit in which a current limiter to limit a current and a voltage limiter to limit the magnitude of a voltage applied to both ends of the current limiter are connected in parallel.

A damage predicting device of a power semiconductor switching element includes a resistor connected to a gate of the power semiconductor switching element, and control circuitry. The control circuitry compares a detection voltage matching a voltage generated between two ends of the resistor and a reference voltage, and predicts that predetermined damage has been accumulated in a gate insulating layer in the power semiconductor switching element when the detection voltage exceeds the reference voltage.

A drive circuit of a voltage-controlled power semiconductor element, including first to fourth switching elements, first and second delay circuits, an overcurrent detection circuit, a slow shutdown detection circuit and a flip-flop. The first switching element turns on upon receiving an off signal. The second switching element is turned on by the first delayed signal generated by the first delay circuit. The third switching element turns on upon receiving a second delayed signal generated by the second delay circuit through the flip-flop. The fourth switching element is turned on by the slow shutdown detection signal generated by the slow shutdown detection circuit. The first to fourth switching elements extract electric charges from the gate terminal of the voltage-controlled power semiconductor element, with first to fourth extracting capabilities, respectively. The first and fourth extracting capabilities are larger than the third extracting capability and smaller than the second extracting capability.