A solid-state relay includes a semiconductor switch and a voltage boost block. The semiconductor switch has a control input, which causes the semiconductor switch to shift from an open, non-conducting position to a closed, conducting position when a voltage is applied to the control input. The voltage boost block includes a boost converter and a ground connector. A voltage output of the semiconductor switch is electrically connected to a voltage input of the boost converter. A voltage output of the boost converter is electrically connected to the control input. The ground connector of the boost converter is electrically connected to a voltage input of the semiconductor switch When the semiconductor switch is in the closed position, the semiconductor switch is maintained in a closed position in the absence of another control signal.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A power converter provides a low-voltage output using a full-bridge fault-tolerant rectification circuit. The output circuit uses controlled switches as rectifiers. A fault detection circuit monitors circuit conditions. Upon detection of a fault, the switches are disabled decoupling the power converter from the system. A common-source dual MOSFET device includes a plurality of elements arranged in alternating patterns on a semiconductor die. A common-source dual synchronous rectifier includes control circuitry powered from the drain to source voltage of the complementary switch. A DC-to-DC transformer converts power from an input source to a load using a fixed voltage transformation ratio. A clamp phase may be used to reduce power losses in the converter at light loads, control the effective output resistance of the converter, effectively regulate the voltage transformation ratio, provide narrow band output regulation, and control the rate of change of output voltage for example during start up. One or more of the transformer windings may be clamped. The converter may use the sine amplitude converter topology. The converter may use common-source dual MOSFET devices and fault detection. The density of point of load power conversion may be increased and the associated power dissipation reduced by removing the input driver circuitry from the point of load where it is not necessary. An output circuit may be located at the point of load providing fault tolerant rectification of the AC power from the secondary winding of a power transformer which may be located nearby the output circuit. The resonant voltage and current waveforms on the primary side of the transformer are readily communicated via an AC bus between the driver circuit and the primary winding of the power transformer. The driver circuit may drive a plurality of transformer-output circuit pairs. The transformer and output circuit may be combined in a single module at the point of load. Alternatively, the output circuit may be integrated into point of load circuitry such as a processor core. The transformer may be deployed near the output circuit.

Methods, systems, and apparatus to facilitate a fault triggered diode emulation mode of a transistor. An example apparatus includes a driver to output a control signal to a gate terminal of a transistor of a power converter; and a diode emulation control circuit to, in response to determining a fault corresponding to the transistor, enable the transistor when current flows in a direction from a source terminal of the transistor to a drain terminal of the transistor.

The present application relates to the field of electronic technology and provides an active diode circuit and an AC/DC power conversion circuit, including a power interface, a drain interface, a control interface, a source interface, a logic unit, a constant current source, and a first switch transistor. A first terminal of the constant current source is connected to the drain interface of the active diode circuit, a second terminal and a third terminal of the constant current source are both connected to the power interface, and a fourth terminal of the constant current source is connected to the logic unit; a first input terminal of the logic unit is connected to the fourth terminal of the constant current source, a second input terminal of the logic unit is connected to the control interface, and an output terminal of the logic unit is connected to a gate electrode of the first switch transistor; and the drain electrode of the first switch transistor is connected to the drain interface of the active diode circuit, and the source electrode of the first switch transistor is connected to the source interface of the active diode circuit. The present application solves the problems of the diode temperature rise of the rectifier bridge and the complex structure of the PFC circuit.

In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit. The time from the input of a signal to the input terminal of the first circuit to the output of a signal from an output terminal of the inverter circuit depends on the potential of the back gate of the second transistor.

Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

A load driving device is configured to reduce erroneous blocking operation in a switch. The load driving device includes: a control unit configured to output a driving signal and a non-driving signal; a first switch unit configured to switch power between a power supply unit and a load to a conductive state and a non-conductive state, and switch the power path to a conductive state when a difference between a potential of the first input line and a potential of a conducting path on the load side is greater than a predetermined value; and a second switch unit configured to connect a power supply to the first input line into a conductive state upon the control unit outputting the driving signal, and to block conduction between the power supply path and the first input line upon the control unit outputting the non-driving signal.