Systems, methods, and apparatuses are provided for a single or multi-dimmer system having improved reliable connectivity between a dimmer assembly and a switch or between two or more dimmer assemblies.

A driver circuit for controlling a P-channel MOSFET includes a first voltage divider connected to a source terminal of the P-channel MOSFET, a first sub-transistor including a first collector terminal, a first emitter terminal and a first base terminal, the first collector terminal is connected to the first voltage divider, a second sub-transistor including a second collector terminal, a second emitter terminal and a second base terminal, the second emitter terminal is connected to a gate terminal of the P-channel MOSFET, and the second base terminal is connected to a first connection node, a third sub-transistor including a third collector terminal, a third emitter terminal and a third base terminal, the third emitter terminal is connected to the second emitter terminal, and the third collector terminal is connected to a ground, and a first resistor connected between the second collector terminal and the second emitter terminal.

A controller for a power converter having at least a first switch and a second switch. Each switch is a transistor with a collector terminal, an emitter terminal, and a base terminal. The controller is connectable to the base terminals of the first and second switches to provide a base current to the base terminals of the first and second switches, and connectable to the emitter terminals of the first and second switches to provide a short-circuit between the base and emitter terminals of the first and second switches. The controller also comprises a timing circuit for controlling the provision of the base current and the short-circuit in a sequence. An associated method is also provided.

A driver circuit for controlling a P-channel MOSFET includes a first voltage divider connected to a source terminal of the P-channel MOSFET, a first sub-transistor including a first collector terminal, a first emitter terminal and a first base terminal, the first collector terminal is connected to the first voltage divider, a second sub-transistor including a second collector terminal, a second emitter terminal and a second base terminal, the second emitter terminal is connected to a gate terminal of the P-channel MOSFET, and the second base terminal is connected to a first connection node, a third sub-transistor including a third collector terminal, a third emitter terminal and a third base terminal, the third emitter terminal is connected to the second emitter terminal, and the third collector terminal is connected to a ground, and a first resistor connected between the second collector terminal and the second emitter terminal.

Systems, methods, and apparatuses are provided for a single or multi-dimmer system having improved reliable connectivity between a dimmer assembly and a switch or between two or more dimmer assemblies.

A semiconductor device including a first semiconductor chip, a second semiconductor chip, the junction temperature of which becomes higher than that of the first semiconductor chip during switching of the semiconductor device, a collector pattern electrically connected to a collector of the first semiconductor chip and a collector of the second semiconductor chip, an emitter pattern electrically connected to an emitter of the first semiconductor chip and an emitter of the second semiconductor chip, a gate pattern electrically connected to a gate of the first semiconductor chip, a first diode having an anode electrically connected to the gate pattern and a cathode electrically connected to a gate of the second semiconductor chip and a second diode connected in reverse parallel with the first diode.

A semiconductor device including a first semiconductor chip, a second semiconductor chip, the junction temperature of which becomes higher than that of the first semiconductor chip during switching of the semiconductor device, a collector pattern electrically connected to a collector of the first semiconductor chip and a collector of the second semiconductor chip, an emitter pattern electrically connected to an emitter of the first semiconductor chip and an emitter of the second semiconductor chip, a gate pattern electrically connected to a gate of the first semiconductor chip, a first diode having an anode electrically connected to the gate pattern and a cathode electrically connected to a gate of the second semiconductor chip and a second diode connected in reverse parallel with the first diode.

A transmitter includes: an output driver that outputs differential signals to differential signal lines; first termination resistors and a first switch which are provided in series between a first reference voltage input terminal to which a reference voltage is inputted and the differential signal lines; a pulse generator that outputs a common-mode pulse to the differential signal lines during a period during which a pulse output instruction signal is at a significant level; and a detector that outputs a detection result signal indicating a magnitude relationship between a voltage level of the common-mode pulse and a threshold, during a period during which the pulse output instruction signal is at a significant level, and outputs a detection result signal indicating that the voltage level of the common-mode pulse does not exceed the threshold, during a period during which the pulse output instruction signal is at a non-significant level.

A transmitter includes: an output driver that outputs differential signals to differential signal lines; first termination resistors and a first switch which are provided in series between a first reference voltage input terminal to which a reference voltage is inputted and the differential signal lines; a pulse generator that outputs a common-mode pulse to the differential signal lines; a second switch provided between the differential signal lines and the pulse generator; a detector that detects, after generation of the common-mode pulse starts, timing at which a voltage level of the common-mode pulse exceeds a threshold; and a controller that places the second switch in an on state to connect the pulse generator to the differential signal lines, and powers down the output driver and then places the first switch in an off state to allow the pulse generator to output the common-mode pulse to the differential signal lines.

The present disclosure provides an IGBT driving circuit, including an optocoupler chip and a power amplification circuit. The optocoupler chip includes an isolation amplification unit and a fault protection unit, and the fault protection unit includes a desaturation module and a fault feedback module. The desaturation module is configured to transmit a warning signal to the fault feedback module when detecting that a potential of a collector of the IGBT is overhigh or the potential of the collector of the IGBT changes overfast. The fault feedback module is configured to transmit a fault control signal to the external controller after receiving the warning signal so as to control the external driving signal outputted by the external controller and enable the isolation amplification unit to output an IGBT driving signal for controlling a shutdown of the IGBT.