Embodiments of input supply circuits and methods for operating an input supply circuit are described. In one embodiment, an input supply circuit includes a bias circuit configured to define a voltage threshold in response to an input signal, and an input buffer configured to generate an output signal in response to the voltage threshold. Other embodiments are also described.

A vehicle analog comparator circuit for communication interfaces designed to detect an actuation of an actor. The circuit comprises a unit for producing a supply voltage for supplying the actor, a unit for producing a reference voltage to be compared with the supply voltage, a transistor input stage, a node point EDMx between the actor, the unit for producing a supply voltage and the transistor input stage, and a digital evaluation unit to process the output signal from the transistor input stage such that whether or not the actor is actuated is detected. The transistor input stage comprises a transistor circuit with a first transistor is connected to the node point EDMx, and a second transistor connected to the reference voltage. A collector resistance for limiting the collector current of the second transistor, as well as a base resistance for the two transistors. Alternatively, a current mirror is provided.

A vehicle analog comparator circuit for communication interfaces designed to detect an actuation of an actor. The circuit comprises a unit for producing a supply voltage for supplying the actor, a unit for producing a reference voltage to be compared with the supply voltage, a transistor input stage, a node point EDMx between the actor, the unit for producing a supply voltage and the transistor input stage, and a digital evaluation unit to process the output signal from the transistor input stage such that whether or not the actor is actuated is detected. The transistor input stage comprises a transistor circuit with a first transistor is connected to the node point EDMx, and a second transistor connected to the reference voltage. A collector resistance for limiting the collector current of the second transistor, as well as a base resistance for the two transistors. Alternatively, a current mirror is provided.

Provided is a switching apparatus, including: a first semiconductor switching device of IGBT, and a second semiconductor switching device of a different type from IGBT, which are electrically connected in parallel; and a control unit configured to turn on the second semiconductor switching device before the first semiconductor switching device, wherein a maximum rated current of the second semiconductor switching device is greater than a maximum rated current of the first semiconductor switching device.

A multiplexing circuit includes an output terminal, a first type transistor, a second type transistor and an impedance circuit. The output terminal is arranged to output a serial output signal. The first type transistor is coupled between a first reference voltage and the output terminal. The second type transistor is coupled between a second reference voltage and the output terminal, wherein the first type is different from the second type. The impedance circuit is arranged to provide an impedance between a gate terminal of the first type transistor and the output terminal.

A multiplexing circuit includes an output terminal, a first type transistor, a second type transistor and an impedance circuit. The output terminal is arranged to output a serial output signal. The first type transistor is coupled between a first reference voltage and the output terminal. The second type transistor is coupled between a second reference voltage and the output terminal, wherein the first type is different from the second type. The impedance circuit is arranged to provide an impedance between a gate terminal of the first type transistor and the output terminal.

A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

A qubit system is provided wherein successive sets of M RF pulses are generated simultaneously, for application to qubit circuits in a plurality of N groups of M qubit circuits. M switching multiplexer circuits are used, each to pass a respective one of the M RF pulses in the set to a selected one of a plurality of N M to one RF combiners in a multiplexing mode. Combined RF pulses at M different RF frequencies are transmitted from each of the N combiners to a transmission structure for a respective one of the groups. Individual ones of the combined RF pulses are coupled from the transmission structure for the group to respective ones of the qubit circuits of the groups via respective frequency selective filters. In a broadcast mode the M switching multiplexer circuits are used to transmit the simultaneous pulses to all of RF combiners.

A qubit system is provided wherein successive sets of M RF pulses are generated simultaneously, for application to qubit circuits in a plurality of N groups of M qubit circuits. M switching multiplexer circuits are used, each to pass a respective one of the M RF pulses in the set to a selected one of a plurality of N M to one RF combiners in a multiplexing mode. Combined RF pulses at M different RF frequencies are transmitted from each of the N combiners to a transmission structure for a respective one of the groups. Individual ones of the combined RF pulses are coupled from the transmission structure for the group to respective ones of the qubit circuits of the groups via respective frequency selective filters. In a broadcast mode the M switching multiplexer circuits are used to transmit the simultaneous pulses to all of RF combiners.