Provided is a phase self-correction circuit, including a trigger signal operation module and a signal phase correction module. The trigger signal operation module and the signal phase correction module are both composed of a plurality of discrete components. The trigger signal operation module is configured to perform a logical operation on an input phase standard reference signal and actual transmission signal, to obtain a target trigger signal for triggering the signal phase correction module; and the signal phase correction module is configured to output, based on trigger modes of the target trigger signal and the actual transmission signal, a self-correction transmission signal with the same waveform as that of the phase standard reference signal, to realize phase self-correction on the actual transmission signal.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.

A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, a buffer, and an RC circuit coupled in series with the buffer between the input terminal and the output terminal. The RC circuit includes a first transistor and an RC network including a resistor and a capacitor, the first transistor is coupled in series with the resistor between a power supply node and a reference node, and the buffer and the RC circuit are configured to generate an output signal based on the input signal.

A method uses a distributed data acquisition system with multiple, physically unconnected, data acquisition units, that can be in wireless communication with a remote host, to timestamp measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. A current absolute time is derived from messages received from a satellite radio beacon positioning system (GPS). Measurement data is sampled by each unit at a specified sampling rate. Using hardware logic, batches of sampled data are associated with corresponding timestamps representing the absolute time at which the data was sampled. Data and timestamps may be transmitted to the host. A time offset bias is compensated by comparing timestamps against a nominal time based on start time and nominal sampling rate. The sampling clock rate may be disciplined using time pulses from the GPS receiver. An initial start of data sampling by all units can also be synchronized.

According to one embodiment, a semiconductor integrated circuit device comprises first and second transistors having control terminals receiving an input signal and an inversion signal of the input signal, third and fourth transistors having control terminals receiving the input signal and the inversion signal, first and second inverters in which outputs are connected to inputs of other converters, and a fifth transistor connected to the first to fourth transistors. The third and fourth transistors are connected to outputs of the second and the first inverters. Clock signal is supplied to the fifth transistor.

Embodiments include a memory device with an improved calibration circuit. Memory device input/output pins include delay lines for adjusting the delay in each memory input/output signal path. The delay adjustment circuitry includes digital delay lines for adjusting this delay. Further, each digital delay line is calibrated via a digital delay line locked loop which enables adjustment of the delay through the digital delay line in fractions of a unit interval across variations due to differences in manufacturing process, operating voltage, and operating temperature. The disclosed techniques calibrate the digital delay lines by measuring both the high phase and the low phase of the clock signal. As a result, the disclosed techniques compensate for duty cycle distortion by combining the calibration results from both phases of the clock signal. The disclosed techniques thereby result in lower calibration error relative to approaches that measure only one phase of the clock signal.

A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.

Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device has sub-circuits having different clock domains. The clock domains form a hierarchical structure. The clock distribution network has a clock source to provide a global clock signal. A programmable delay line associated with a sub-circuit generates a local clock signal for the sub-circuit by delaying the signal. A global skew control circuit can manage clock skew between the local clock signals. The global skew control circuit may adjust a delay, determine initial operations for the delay lines, verify whether it is possible to perform the initial operations, and perform a correction operation. The correction operation can include correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks.

A zero current detection system for a switching regulator is provided. The switching includes an inductor. In the zero current detection system, a comparator has a positive input coupled to a terminal of the inductor and an output terminal for outputting a comparison result signal; a first signal latch circuit has a clock terminal for receiving the comparison result signal and outputting a latched output signal; a delay line module starts counting upon receipt of the latched output signal, and then outputs a zero current detection signal after counting a delay time; in response to the zero current detection signal, a voltage sampling module samples a node voltage at two different time points, to generate two sampling voltages; a delay control module adjusts the delay time of the delay line module according to the two sampling voltages.