A nuclear reaction detection device includes an FPGA (Field Programmable Gate Array) 100 which is arranged in an environment in which particle radiation is incident, and includes a user circuit 101 configured to output a value different from that in a normal state, if an SEU (Single Event Upset) occurs in a semiconductor element included in the FPGA, and an SEF detection unit 210 which detects that an abnormal operation (SEF) has occurred in the user circuit based on the output value from the user circuit 101 of the FPGA 100.

The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.

A flip-flop and latch circuit is disclosed. The circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the circuit

The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

A power distribution device includes an input, an output, a power switch controller, and a voltage isolation device. The power distribution device includes, and is designed to provide power to, for example, non-radiation-tolerant or non-radiation hardened components for use in low Earth orbit (LEO) missions. The input is configured to receive power from a power source. The output is configured to provide the power to an electrical load. The power switch controller is configured to selectively operate the power distribution device in a first mode responsive to a first event, and to selectively operate the power distribution device in a second mode responsive to a second event. The voltage isolation device includes a plurality of switches configured, in the first mode, to pass the power between the input and the output, and, in the second mode, to interrupt the passage of the power between the input and the output.

A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.

According to embodiments of the present invention, a circuit is provided. The circuit includes forming a first electrical device having a first region of a first conductivity type, forming a second electrical device having a second region of a second conductivity type, and electrically coupling the first region and the second region to each other, wherein one of the first and second regions is arranged to at least substantially surround the other of the first and second regions. According to further embodiments of the present invention, a method of forming a circuit is also provided.

Techniques to compensate non-radiation hardened components for changes or degradation in performance that result from exposure to radiation. During testing and modeling phase, a component's performance may be characterized as a result of the exposure to radiation. In some examples, some performance characteristics, such as voltage response, frequency response, gain, leakage or other characteristics, may change as the component's exposure to an amount of radiation increases. During normal operation, a system may include one or more devices that measure the amount of radiation to which the system may be subjected, such as a radiation dosimeter. The system may compensate the non-radiation hardened component based on the amount of radiation received the known component performance change caused by radiation as determined during the modeling phase.

A method for selecting components in a radiation tolerant electronic system, comprising, determining ionizing radiation responses of COTS devices under various radiation conditions, selecting a subset of the COTS devices whose radiation responses satisfy threshold radiation levels, applying mathematical models of the COTS devices for post-irradiation conditions to determine radiation responses to ionizing radiation; implementing a radiation-tolerant architecture using COTS devices from the selected subset, the implemented circuit may be tested for robustness to ionizing radiation effects without repeated destructive tests of the hardware circuit by using the mathematical models for simulating response to the ionizing radiation, and implementing a multi-layer shielding to protect the implemented circuit under various radiation conditions.

An integrated circuit system includes: a storage element which stores in advance a plurality of pieces of circuit information and startup control circuit information used to configure a startup control logic circuit for selecting circuit information that has not failed in configuring a logic circuit; and an integrated circuit which, at the time of startup or when configuration of the logic circuit based on any of the plurality of pieces of circuit information has failed, configures the startup control logic circuit by reading the startup control circuit information from the storage element, causes the configured startup control logic circuit to select the circuit information that has not failed in configuring the logic circuit, reads the circuit information selected by the startup control logic circuit from the storage element, and configures the logic circuit according to the circuit information.