A bootstrapped switch is provided. The bootstrapped switch includes a first transistor, a second transistor, a capacitor and five switches. The first transistor receives an input voltage and outputs an output voltage. A first terminal of the second transistor receives the input voltage, and a second terminal of the second transistor is coupled to a first terminal of the capacitor. In a first clock phase, the capacitor is being charged. In a second clock phase, the control terminal of the first transistor and the control terminal of the second transistor are substantially equipotential with a second terminal of the capacitor. The control terminal of the first transistor and the control terminal of the second transistor are coupled to the power supply voltage within a predetermined time before the terminal of the first clock phase or within a predetermined time after the start of the second clock phase.

A bootstrapped switch is provided. The bootstrapped switch includes a first transistor, a second transistor, a capacitor and five switches. The first transistor receives an input voltage and outputs an output voltage. A first terminal of the second transistor receives the input voltage, and a second terminal of the second transistor is coupled to a first terminal of the capacitor. In a first clock phase, the capacitor is being charged. In a second clock phase, the control terminal of the first transistor and the control terminal of the second transistor are substantially equipotential with a second terminal of the capacitor. The control terminal of the first transistor and the control terminal of the second transistor are coupled to the power supply voltage within a predetermined time before the terminal of the first clock phase or within a predetermined time after the start of the second clock phase.

A gate on array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. A pull-up module includes a first switch, a second switch, a third switch and a fourth switch. When a n.sup.th stage signal STn corresponds to a high voltage level, the third switch is turned on and residual charges of the first switch, the second switch and the third switch are released through an output end of the fourth switch to prevent the residual charges from influencing performances of the first switch, the second switch, the third switch and the fourth switch.

A high-side switching transistor of a rectifier circuit is driven by a high-side driver circuit to supply current to an output node. The high-side driver circuit is powered between a capacitive bootstrap node and the output node. A boot charge circuit charges the bootstrap capacitor by supplying current to the bootstrap node. The boot charge circuit includes: a first current path that selectively supplies a first charging current to the bootstrap node when the rectifier circuit is operating in a switching mode; and a second current path that selectively supplies a second charging current to the bootstrap node when the rectifier circuit is operating in a reset mode.

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

An electrical circuit includes a ground-referenced transistor and a non-ground-referenced transistor configured in a half-bridge topology. The non-ground-referenced power transistor has a first conducting electrode coupled to a high voltage power supply, a control electrode coupled to a high-side pre-driver, and a second conducting electrode coupled to a switch node. The electrical circuit further includes a boot-strapped capacitor having a bottom plate coupled to the second conducting electrode and a top plate coupled to the high-side pre-driver, and an interface coupled to a first sense device for sensing a voltage at the top plate, a second sense device for sensing a voltage at the bottom plate, and a charging device for selectively increasing the voltage at the top plate. The interface controls the charging device based on the voltage at the top plate and the voltage at the bottom plate.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.

A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDDV thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.

According to an aspect, a current mode logic circuit comprise a first transistor to which an input voltage is applied, a second transistor connected in parallel with the first transistor; and a voltage sampling circuit which is connected to the first transistor and the second transistor and resets an output voltage output by integrating the input voltage for a predetermined set time (T) in a manner in which the output voltage is integrated in a direction opposite to a direction in which the input voltage is integrated for the predetermined set time (T).