Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

A CAM array of compare memory cell circuits includes a decode column corresponding to each set, and each set includes at least one row of the compare memory cell circuits. Each decode column receives a set clock signal addressing the corresponding set and generates a set match signal in each row of the corresponding set. A column compare circuit generates compare data indicating a bit of a compare tag. A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row. Circuits and loads in a decode column employed to generate the set clock signal correspond to circuits generating the row match signal in each column of the CAM array to reduce a timing margin of the match indication and decrease the access time for the CAM array.

A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

An example adapter device includes a host-side connector to connect to a host device, the host-side connector including a host-side electrical contact to connect to a corresponding electrical contact of the host device. The adapter device further includes a storage-side connector to connect to storage devices operable under different protocols, the storage-side connector including a storage-side electrical contact to connect to a connected storage device. The adapter device further includes a circuit to apply a bias voltage to the host-side electrical contact. The host-side electrical contact is to provide a protocol-indicating voltage to indicate to the host device a protocol of the connected storage device. The protocol-indicating voltage is dependent on the connected storage device's influence on the bias voltage.

A memory device and operating method of the memory device are provided. The memory device comprises a memory cell storing data based on a first voltage, a row decoder selecting a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal, which is for generating a wordline voltage to be provided to the row decoder. The wordline predecoder is driven by the first voltage and a second voltage, which is different from the first voltage, receives a row address signal, associated with selecting the wordline, and an internal clock signal associated with adjusting operating timings of elements included in the memory device. The wordline predecoder performs a NAND operation on the row address signal and the internal clock signal, and provides the “predec” signal generated based on a result of the NAND operation to the row decoder.

A repeater for open-drain bus communication and a system including the same is provided. The repeater includes at least one repeating unit having an A-side terminal connected to an A-side open-drain bus, and a B-side terminal electrically connected to a B-side open-drain bus. The repeater has a first mode to receive a signal at the A-side and to produce a signal at the B-side. The repeating unit includes a B-side accelerator element connected to the B-side terminal. The repeating unit when in a first mode includes a first control unit to, control the B-side accelerator element to pull up a voltage at the B-side when the voltage at the A-side surpasses a first threshold voltage during a rising edge of the voltage, and to subsequently control the B-side accelerator element to stop pulling up the voltage at the B-side when the voltage at the B-side surpasses a second threshold voltage.

A repeater for open-drain bus communication and a system including the same is provided. The bus repeater includes an A-to-B buffer to receive the signal at the A-side terminal and to produce a first buffered signal, a B-side pull-down control unit to produce a first control signal based on the received first buffered signal, and a B-side pull-down element to pull down the voltage at the B-side terminal based on the first control signal. The B-side pull-down element includes a B-side pull-down transistor that is arranged in between the B-side terminal and a B-side ground reference terminal. The first control signal controls a voltage at the control terminal of the B-side pull-down transistor. The B-side pull-down control unit includes a B-side comparing unit to compare the voltage at the B-side terminal to a first reference voltage, and to generate the first control signal based on a result of the comparison.

A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.

An off chip driver circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes several first transistors and a first resistance circuit coupled between the first transistors and a input/output pad. The first transistors generate a first voltage to the first resistance circuit. The first resistance circuit transmits, in response to a first control signal, the first voltage to the input/output pad and to have a variable resistance according to the first control signal. The pull-down circuit includes several second transistors and a second resistance circuit coupled between the second transistors and the input/output pad. The second transistors generate a second voltage to the second resistance circuit. The second resistance circuit transmits, in response to a second control signal, the second voltage to the input/output pad and to have a variable resistance according to the second control signal.